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Custom DAGCombine for and/or/xor are for all ARMs.

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The 'select' transformations apply to all ARM architectures and don't
require hasV6T2Ops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163396 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen committed 2012-09-07 17:34:15 +00:00
1 parent 39646d96e7
commit a7390fadba
1 file changed
+3 -6
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lib/Target/ARM/ARMISelLowering.cpp
+3 -6
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@@ -796,12 +796,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setTargetDAGCombine(ISD::ADD);
setTargetDAGCombine(ISD::SUB);
setTargetDAGCombine(ISD::MUL);
if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) {
setTargetDAGCombine(ISD::AND);
setTargetDAGCombine(ISD::OR);
setTargetDAGCombine(ISD::XOR);
}
setTargetDAGCombine(ISD::AND);
setTargetDAGCombine(ISD::OR);
setTargetDAGCombine(ISD::XOR);
if (Subtarget->hasV6Ops())
setTargetDAGCombine(ISD::SRL);