mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-06-29 00:30:47 +00:00
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
Also, fix predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
bf19dba2d4
commit
a796d90c0e
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@ -88,6 +88,11 @@ class MipsAsmParser : public MCTargetAsmParser {
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MipsAsmParser::OperandMatchResultTy
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parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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bool parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands, int RegKind);
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MipsAsmParser::OperandMatchResultTy
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parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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MipsAsmParser::OperandMatchResultTy
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parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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@ -179,6 +184,10 @@ class MipsAsmParser : public MCTargetAsmParser {
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return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
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}
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bool isN64() const {
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return STI.getFeatureBits() & Mips::FeatureN64;
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}
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int matchRegisterName(StringRef Symbol, bool is64BitReg);
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int matchCPURegisterName(StringRef Symbol);
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@ -245,6 +254,7 @@ private:
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k_Memory,
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k_PostIndexRegister,
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k_Register,
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k_PtrReg,
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k_Token
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} Kind;
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@ -284,6 +294,11 @@ public:
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Inst.addOperand(MCOperand::CreateReg(getReg()));
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}
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void addPtrRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getPtrReg()));
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}
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void addExpr(MCInst &Inst, const MCExpr *Expr) const{
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// Add as immediate when possible. Null MCExpr = 0.
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if (Expr == 0)
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@ -313,6 +328,7 @@ public:
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bool isImm() const { return Kind == k_Immediate; }
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bool isToken() const { return Kind == k_Token; }
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bool isMem() const { return Kind == k_Memory; }
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bool isPtrReg() const { return Kind == k_PtrReg; }
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StringRef getToken() const {
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assert(Kind == k_Token && "Invalid access!");
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@ -324,8 +340,13 @@ public:
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return Reg.RegNum;
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}
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unsigned getPtrReg() const {
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assert((Kind == k_PtrReg) && "Invalid access!");
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return Reg.RegNum;
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}
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void setRegKind(RegisterKind RegKind) {
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assert((Kind == k_Register) && "Invalid access!");
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assert((Kind == k_Register || Kind == k_PtrReg) && "Invalid access!");
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Reg.Kind = RegKind;
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}
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@ -361,6 +382,14 @@ public:
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return Op;
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}
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static MipsOperand *CreatePtrReg(unsigned RegNum, SMLoc S, SMLoc E) {
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MipsOperand *Op = new MipsOperand(k_PtrReg);
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Op->Reg.RegNum = RegNum;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
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MipsOperand *Op = new MipsOperand(k_Immediate);
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Op->Imm.Val = Val;
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@ -1289,6 +1318,68 @@ MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
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return MatchOperand_Success;
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}
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bool
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MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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int RegKind) {
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// If the first token is not '$' we have an error.
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if (Parser.getTok().isNot(AsmToken::Dollar))
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return false;
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SMLoc S = Parser.getTok().getLoc();
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Parser.Lex();
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AsmToken::TokenKind TkKind = getLexer().getKind();
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int Reg;
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if (TkKind == AsmToken::Integer) {
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Reg = matchRegisterByNumber(Parser.getTok().getIntVal(),
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regKindToRegClass(RegKind));
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if (Reg == -1)
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return false;
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} else if (TkKind == AsmToken::Identifier) {
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if ((Reg = matchCPURegisterName(Parser.getTok().getString().lower())) == -1)
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return false;
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Reg = getReg(regKindToRegClass(RegKind), Reg);
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} else {
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return false;
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}
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MipsOperand *Op = MipsOperand::CreatePtrReg(Reg, S, Parser.getTok().getLoc());
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Op->setRegKind((MipsOperand::RegisterKind)RegKind);
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Operands.push_back(Op);
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Parser.Lex();
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return true;
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}
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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MipsOperand::RegisterKind RegKind = isN64() ? MipsOperand::Kind_GPR64 :
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MipsOperand::Kind_GPR32;
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// Parse index register.
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if (!parsePtrReg(Operands, RegKind))
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return MatchOperand_NoMatch;
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// Parse '('.
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if (Parser.getTok().isNot(AsmToken::LParen))
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return MatchOperand_NoMatch;
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Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
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Parser.Lex();
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// Parse base register.
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if (!parsePtrReg(Operands, RegKind))
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return MatchOperand_NoMatch;
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// Parse ')'.
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if (Parser.getTok().isNot(AsmToken::RParen))
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return MatchOperand_NoMatch;
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Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
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Parser.Lex();
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return MatchOperand_Success;
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}
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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int RegKind) {
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@ -35,14 +35,18 @@ public:
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///
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MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
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bool bigEndian) :
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MCDisassembler(STI), RegInfo(Info), isBigEndian(bigEndian) {}
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MCDisassembler(STI), RegInfo(Info),
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IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
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virtual ~MipsDisassemblerBase() {}
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const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
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bool isN64() const { return IsN64; }
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private:
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OwningPtr<const MCRegisterInfo> RegInfo;
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bool IsN64;
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protected:
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bool isBigEndian;
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};
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@ -103,6 +107,11 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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@ -364,6 +373,16 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
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return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
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return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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@ -348,10 +348,9 @@ class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs GPR32Opnd:$rd);
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dag InOperandList = (ins GPR32Opnd:$base, GPR32Opnd:$index);
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dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
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string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
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list<dag> Pattern = [(set GPR32Opnd:$rd,
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(OpNode GPR32Opnd:$base, GPR32Opnd:$index))];
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list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
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InstrItinClass Itinerary = itin;
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bit mayLoad = 1;
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}
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@ -171,19 +171,19 @@ class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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[(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
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Itin, FrmFR>;
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class LWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
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class LWXC1_FT<string opstr, RegisterOperand DRC,
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InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
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InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
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InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
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!strconcat(opstr, "\t$fd, ${index}(${base})"),
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[(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> {
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[(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin, FrmFI> {
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let AddedComplexity = 20;
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}
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class SWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
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class SWXC1_FT<string opstr, RegisterOperand DRC,
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InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
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InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
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InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
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!strconcat(opstr, "\t$fs, ${index}(${base})"),
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[(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> {
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[(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, FrmFI> {
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let AddedComplexity = 20;
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}
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@ -378,52 +378,30 @@ let Predicates = [NotFP64bit, HasStdEnc] in {
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// Indexed loads and stores.
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let Predicates = [HasFPIdx, HasStdEnc] in {
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def LWXC1 : LWXC1_FT<"lwxc1", FGR32Opnd, GPR32Opnd, IIFLoad, load>,
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LWXC1_FM<0>;
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def SWXC1 : SWXC1_FT<"swxc1", FGR32Opnd, GPR32Opnd, IIFStore, store>,
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SWXC1_FM<8>;
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def LWXC1 : LWXC1_FT<"lwxc1", FGR32Opnd, IIFLoad, load>, LWXC1_FM<0>;
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def SWXC1 : SWXC1_FT<"swxc1", FGR32Opnd, IIFStore, store>, SWXC1_FM<8>;
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}
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let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
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def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, GPR32Opnd, IIFLoad, load>,
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LWXC1_FM<1>;
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def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, GPR32Opnd, IIFStore, store>,
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SWXC1_FM<9>;
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let Predicates = [HasFPIdx, NotFP64bit, HasStdEnc] in {
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def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, IIFLoad, load>, LWXC1_FM<1>;
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def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, IIFStore, store>, SWXC1_FM<9>;
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}
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let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
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def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, GPR32Opnd, IIFLoad, load>,
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LWXC1_FM<1>;
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def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, GPR32Opnd, IIFStore, store>,
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SWXC1_FM<9>;
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}
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// n64
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let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
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def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32Opnd, GPR64Opnd, IIFLoad, load>,
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LWXC1_FM<0>;
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def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64Opnd, GPR64Opnd, IIFLoad,
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load>, LWXC1_FM<1>;
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def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32Opnd, GPR64Opnd, IIFStore,
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store>, SWXC1_FM<8>;
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def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64Opnd, GPR64Opnd, IIFStore,
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store>, SWXC1_FM<9>;
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let Predicates = [HasFPIdx, IsFP64bit, HasStdEnc],
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DecoderNamespace="Mips64" in {
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def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, IIFLoad, load>, LWXC1_FM<1>;
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def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, IIFStore, store>, SWXC1_FM<9>;
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}
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// Load/store doubleword indexed unaligned.
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let Predicates = [NotMips64, HasStdEnc] in {
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def LUXC1 : LWXC1_FT<"luxc1", AFGR64Opnd, GPR32Opnd, IIFLoad>,
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LWXC1_FM<0x5>;
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def SUXC1 : SWXC1_FT<"suxc1", AFGR64Opnd, GPR32Opnd, IIFStore>,
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SWXC1_FM<0xd>;
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let Predicates = [NotFP64bit, HasStdEnc] in {
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def LUXC1 : LWXC1_FT<"luxc1", AFGR64Opnd, IIFLoad>, LWXC1_FM<0x5>;
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def SUXC1 : SWXC1_FT<"suxc1", AFGR64Opnd, IIFStore>, SWXC1_FM<0xd>;
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}
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let Predicates = [HasMips64, HasStdEnc],
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DecoderNamespace="Mips64" in {
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def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, GPR32Opnd, IIFLoad>,
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LWXC1_FM<0x5>;
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def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, GPR32Opnd, IIFStore>,
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SWXC1_FM<0xd>;
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let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace="Mips64" in {
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def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, IIFLoad>, LWXC1_FM<0x5>;
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def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, IIFStore>, SWXC1_FM<0xd>;
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}
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/// Floating-point Aritmetic
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@ -279,6 +279,11 @@ def MipsMemAsmOperand : AsmOperandClass {
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let ParserMethod = "parseMemOperand";
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}
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def PtrRegAsmOperand : AsmOperandClass {
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let Name = "PtrReg";
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let ParserMethod = "parsePtrReg";
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}
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// Address operand
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def mem : Operand<iPTR> {
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let PrintMethod = "printMemOperand";
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@ -297,6 +302,8 @@ def mem_ea : Operand<iPTR> {
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def PtrRC : Operand<iPTR> {
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let MIOperandInfo = (ops ptr_rc);
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let DecoderMethod = "DecodePtrRegisterClass";
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let ParserMatchClass = PtrRegAsmOperand;
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}
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// size operand of ext instruction
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@ -11,3 +11,12 @@
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# CHECK: mtlo $21, $ac3
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0x13 0x18 0xa0 0x02
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# CHECK: lbux $10, $20($26)
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0x8a 0x51 0x54 0x7f
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# CHECK: lhx $11, $21($27)
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0x0a 0x59 0x75 0x7f
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# CHECK: lwx $12, $22($gp)
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0x0a 0x60 0x96 0x7f
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@ -242,6 +242,9 @@
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# CHECK: lui $6, 17767
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0x3c 0x06 0x45 0x67
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# CHECK: luxc1 $f0, $6($5)
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0x4c 0xa6 0x00 0x05
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# CHECK: lw $4, 24($5)
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0x8c 0xa4 0x00 0x18
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@ -254,6 +257,9 @@
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# CHECK: lwr $3, 16($5)
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0x98 0xa3 0x00 0x10
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# CHECK: lwxc1 $f20, $12($14)
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0x4d 0xcc 0x05 0x00
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# CHECK: madd $6, $7
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0x70 0xc7 0x00 0x00
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@ -404,6 +410,9 @@
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# CHECK: subu $4, $3, $5
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0x00 0x65 0x20 0x23
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# CHECK: suxc1 $f4, $24($5)
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0x4c 0xb8 0x20 0x0d
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# CHECK: sw $4, 24($5)
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0xac 0xa4 0x00 0x18
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@ -416,6 +425,9 @@
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# CHECK: swr $6, 16($7)
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0xb8 0xe6 0x00 0x10
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# CHECK: swxc1 $f26, $18($22)
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0x4e 0xd2 0xd0 0x08
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# CHECK: sync 7
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0x00 0x00 0x01 0xcf
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@ -242,6 +242,9 @@
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# CHECK: lui $6, 17767
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0x67 0x45 0x06 0x3c
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# CHECK: luxc1 $f0, $6($5)
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0x05 0x00 0xa6 0x4c
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||||
# CHECK: lw $4, 24($5)
|
||||
0x18 0x00 0xa4 0x8c
|
||||
|
||||
|
|
@ -254,6 +257,9 @@
|
|||
# CHECK: lwr $3, 16($5)
|
||||
0x10 0x00 0xa3 0x98
|
||||
|
||||
# CHECK: lwxc1 $f20, $12($14)
|
||||
0x00 0x05 0xcc 0x4d
|
||||
|
||||
# CHECK: madd $6, $7
|
||||
0x00 0x00 0xc7 0x70
|
||||
|
||||
|
|
@ -404,6 +410,9 @@
|
|||
# CHECK: subu $4, $3, $5
|
||||
0x23 0x20 0x65 0x00
|
||||
|
||||
# CHECK: suxc1 $f4, $24($5)
|
||||
0x0d 0x20 0xb8 0x4c
|
||||
|
||||
# CHECK: sw $4, 24($5)
|
||||
0x18 0x00 0xa4 0xac
|
||||
|
||||
|
|
@ -416,6 +425,9 @@
|
|||
# CHECK: swr $6, 16($7)
|
||||
0x10 0x00 0xe6 0xb8
|
||||
|
||||
# CHECK: swxc1 $f26, $18($22)
|
||||
0x08 0xd0 0xd2 0x4e
|
||||
|
||||
# CHECK: sync 7
|
||||
0xcf 0x01 0x00 0x00
|
||||
|
||||
|
|
|
|||
|
|
@ -64,3 +64,21 @@
|
|||
|
||||
# CHECK: sd $6, 17767($zero)
|
||||
0xfc 0x06 0x45 0x67
|
||||
|
||||
# CHECK: luxc1 $f0, $6($5)
|
||||
0x4c 0xa6 0x00 0x05
|
||||
|
||||
# CHECK: lwxc1 $f20, $12($14)
|
||||
0x4d 0xcc 0x05 0x00
|
||||
|
||||
# CHECK: suxc1 $f4, $24($5)
|
||||
0x4c 0xb8 0x20 0x0d
|
||||
|
||||
# CHECK: swxc1 $f26, $18($22)
|
||||
0x4e 0xd2 0xd0 0x08
|
||||
|
||||
# CHECK: ldxc1 $f2, $2($10)
|
||||
0x4d 0x42 0x00 0x81
|
||||
|
||||
# CHECK: sdxc1 $f8, $4($25)
|
||||
0x4f 0x24 0x40 0x09
|
||||
|
|
|
|||
|
|
@ -64,3 +64,21 @@
|
|||
|
||||
# CHECK: sd $6, 17767($zero)
|
||||
0x67 0x45 0x06 0xfc
|
||||
|
||||
# CHECK: luxc1 $f0, $6($5)
|
||||
0x05 0x00 0xa6 0x4c
|
||||
|
||||
# CHECK: lwxc1 $f20, $12($14)
|
||||
0x00 0x05 0xcc 0x4d
|
||||
|
||||
# CHECK: suxc1 $f4, $24($5)
|
||||
0x0d 0x20 0xb8 0x4c
|
||||
|
||||
# CHECK: swxc1 $f26, $18($22)
|
||||
0x08 0xd0 0xd2 0x4e
|
||||
|
||||
# CHECK: ldxc1 $f2, $2($10)
|
||||
0x81 0x00 0x42 0x4d
|
||||
|
||||
# CHECK: sdxc1 $f8, $4($25)
|
||||
0x09 0x40 0x24 0x4f
|
||||
|
|
|
|||
|
|
@ -22,6 +22,10 @@
|
|||
# CHECK: precr_sra_r.ph.w $25, $26, 0 # encoding: [0x7f,0x59,0x07,0xd1]
|
||||
# CHECK: precr_sra_r.ph.w $25, $26, 31 # encoding: [0x7f,0x59,0xff,0xd1]
|
||||
|
||||
# CHECK: lbux $10, $20($26) # encoding: [0x7f,0x54,0x51,0x8a]
|
||||
# CHECK: lhx $11, $21($27) # encoding: [0x7f,0x75,0x59,0x0a]
|
||||
# CHECK: lwx $12, $22($gp) # encoding: [0x7f,0x96,0x60,0x0a]
|
||||
|
||||
# CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x43,0x18,0x18]
|
||||
# CHECK: multu $ac2, $4, $5 # encoding: [0x00,0x85,0x10,0x19]
|
||||
# CHECK: madd $ac1, $6, $7 # encoding: [0x70,0xc7,0x08,0x00]
|
||||
|
|
@ -50,6 +54,10 @@
|
|||
precr_sra_r.ph.w $25,$26,0
|
||||
precr_sra_r.ph.w $25,$26,31
|
||||
|
||||
lbux $10, $s4($26)
|
||||
lhx $11, $s5($27)
|
||||
lwx $12, $s6($28)
|
||||
|
||||
mult $ac3, $2, $3
|
||||
multu $ac2, $4, $5
|
||||
madd $ac1, $6, $7
|
||||
|
|
|
|||
|
|
@ -165,6 +165,8 @@
|
|||
# CHECK: movf.s $f4, $f6, $fcc5 # encoding: [0x11,0x31,0x14,0x46]
|
||||
# CHECK: luxc1 $f0, $6($5) # encoding: [0x05,0x00,0xa6,0x4c]
|
||||
# CHECK: suxc1 $f4, $24($5) # encoding: [0x0d,0x20,0xb8,0x4c]
|
||||
# CHECK: lwxc1 $f20, $12($14) # encoding: [0x00,0x05,0xcc,0x4d]
|
||||
# CHECK: swxc1 $f26, $18($22) # encoding: [0x08,0xd0,0xd2,0x4e]
|
||||
|
||||
cfc1 $a2,$0
|
||||
ctc1 $10,$31
|
||||
|
|
@ -190,5 +192,7 @@
|
|||
movt $4, $5, $fcc4
|
||||
movf.d $f4, $f6, $fcc2
|
||||
movf.s $f4, $f6, $fcc5
|
||||
luxc1 $f0, $a2($a1)
|
||||
suxc1 $f4, $t8($a1)
|
||||
luxc1 $f0, $a2($a1)
|
||||
suxc1 $f4, $t8($a1)
|
||||
lwxc1 $f20, $12($14)
|
||||
swxc1 $f26, $s2($s6)
|
||||
|
|
|
|||
7
test/MC/Mips/mips64-instructions.s
Normal file
7
test/MC/Mips/mips64-instructions.s
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
|
||||
|
||||
# CHECK: ldxc1 $f2, $2($10) # encoding: [0x81,0x00,0x42,0x4d]
|
||||
# CHECK: sdxc1 $f8, $4($25) # encoding: [0x09,0x40,0x24,0x4f]
|
||||
|
||||
ldxc1 $f2, $2($10)
|
||||
sdxc1 $f8, $a0($t9)
|
||||
Loading…
Reference in New Issue
Block a user