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Allow CRC32 instructions to be selected when AVX is enabled.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147411 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-01-01 19:51:58 +00:00
parent de9e4c728e
commit a86bcfb565
3 changed files with 24 additions and 2 deletions
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4
lib/Target/X86/X86InstrFormats.td
View File

@ -436,8 +436,8 @@ class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
// SS42FI - SSE 4.2 instructions with T8XD prefix.
class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern>
: I<o, F, outs, ins, asm, pattern>, T8XD, Requires<[HasSSE42]>;
: I<o, F, outs, ins, asm, pattern>, T8XD, Requires<[HasSSE42orAVX]>;
// SS42AI = SSE 4.2 instructions with TA prefix
class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern>

1
lib/Target/X86/X86InstrInfo.td
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@ -476,6 +476,7 @@ def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
def HasXMM : Predicate<"Subtarget->hasXMM()">;
def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">;
def HasSSE3orAVX : Predicate<"Subtarget->hasSSE3orAVX()">;
def HasSSE42orAVX : Predicate<"Subtarget->hasSSE42orAVX()">;
def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
def HasAES : Predicate<"Subtarget->hasAES()">;

21
test/CodeGen/X86/avx-intrinsics-x86.ll
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@ -2530,3 +2530,24 @@ entry:
ret void
}
declare void @llvm.x86.sse2.clflush(i8*) nounwind
; CHECK: crc32b
define i32 @crc32_32_8(i32 %a, i8 %b) nounwind {
%tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
ret i32 %tmp
}
declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
; CHECK: crc32w
define i32 @crc32_32_16(i32 %a, i16 %b) nounwind {
%tmp = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a, i16 %b)
ret i32 %tmp
}
declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind
; CHECK: crc32l
define i32 @crc32_32_32(i32 %a, i32 %b) nounwind {
%tmp = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a, i32 %b)
ret i32 %tmp
}
declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind