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[mips] Implement MipsRegisterInfo::getRegPressureLimit.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173197 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-01-22 21:34:25 +00:00
parent defaca00b8
commit a88322c283
5 changed files with 31 additions and 7 deletions
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22
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -47,6 +47,28 @@ MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST)
unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
unsigned
MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const {
switch (RC->getID()) {
default:
return 0;
case Mips::CPURegsRegClassID:
case Mips::CPU64RegsRegClassID:
case Mips::DSPRegsRegClassID: {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
return 28 - TFI->hasFP(MF);
}
case Mips::FGR32RegClassID:
return 32;
case Mips::AFGR64RegClassID:
return 16;
case Mips::FGR64RegClassID:
return 32;
}
}
//===----------------------------------------------------------------------===//
// Callee Saved Registers methods
//===----------------------------------------------------------------------===//

2
lib/Target/Mips/MipsRegisterInfo.h
View File

@ -42,6 +42,8 @@ public:
void adjustMipsStackFrame(MachineFunction &MF) const;
/// Code Generation virtual methods...
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const;
const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const uint32_t *getCallPreservedMask(CallingConv::ID) const;

2
test/CodeGen/Mips/i64arg.ll
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@ -17,9 +17,9 @@ entry:
; CHECK: jalr $25
tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
%sub = add nsw i32 %i, -1
; CHECK: lw $25, %call16(ff3)
; CHECK: sw $[[R1]], 28($sp)
; CHECK: sw $[[R0]], 24($sp)
; CHECK: lw $25, %call16(ff3)
; CHECK: or $6, $[[R2]], $zero
; CHECK: or $7, $[[R3]], $zero
; CHECK: jalr $25

10
test/CodeGen/Mips/o32_cc_byval.ll
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@ -12,20 +12,20 @@ define void @f1() nounwind {
entry:
; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)
; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]])
; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]])
; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]])
; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]])
; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]])
; CHECK: sw $[[R6]], 36($sp)
; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]])
; CHECK: sw $[[R5]], 32($sp)
; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]])
; CHECK: sw $[[R4]], 28($sp)
; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]])
; CHECK: sw $[[R3]], 24($sp)
; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]])
; CHECK: sw $[[R7]], 20($sp)
; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]])
; CHECK: sw $[[R2]], 16($sp)
; CHECK: lw $7, 4($[[R0]])
; CHECK: lw $6, %lo(f1.s1)($[[R1]])
; CHECK: lw $7, 4($[[R0]])
%agg.tmp10 = alloca %struct.S3, align 4
call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
call void @callee2(%struct.S2* byval @f1.s2) nounwind

2
test/CodeGen/Mips/tls.ll
View File

@ -21,9 +21,9 @@ entry:
; PIC: jalr $25
; PIC: lw $2, 0($2)
; STATIC: rdhwr $3, $29
; STATIC: lui $[[R0:[0-9]+]], %tprel_hi(t1)
; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
; STATIC: rdhwr $3, $29
; STATIC: addu $[[R2:[0-9]+]], $3, $[[R1]]
; STATIC: lw $2, 0($[[R2]])
}