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R600/SI: Legalize CopyToReg during instruction selection
The instruction emitter will crash if it encounters a CopyToReg node with a non-register operand like FrameIndex. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219428 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -487,9 +487,16 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
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case AMDGPUISD::DIV_SCALE: {
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return SelectDIV_SCALE(N);
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}
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case ISD::CopyToReg: {
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const SITargetLowering& Lowering =
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*static_cast<const SITargetLowering*>(getTargetLowering());
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Lowering.legalizeTargetIndependentNode(N, *CurDAG);
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break;
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}
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case ISD::ADDRSPACECAST:
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return SelectAddrSpaceCast(N);
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}
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return SelectCode(N);
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}
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@ -1920,28 +1920,26 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
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}
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}
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/// \brief Legalize INSERT_SUBREG instructions with frame index operands.
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/// LLVM assumes that all INSERT_SUBREG inputs are registers.
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static void legalizeInsertSubreg(MachineSDNode *InsertSubreg,
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SelectionDAG &DAG) {
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assert(InsertSubreg->getMachineOpcode() == AMDGPU::INSERT_SUBREG);
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/// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
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/// with frame index operands.
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/// LLVM assumes that inputs are to these instructions are registers.
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void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
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SelectionDAG &DAG) const {
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SmallVector<SDValue, 8> Ops;
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for (unsigned i = 0; i < 2; ++i) {
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if (!isa<FrameIndexSDNode>(InsertSubreg->getOperand(i))) {
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Ops.push_back(InsertSubreg->getOperand(i));
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for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
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if (!isa<FrameIndexSDNode>(Node->getOperand(i))) {
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Ops.push_back(Node->getOperand(i));
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continue;
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}
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SDLoc DL(InsertSubreg);
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SDLoc DL(Node);
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Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
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InsertSubreg->getOperand(i).getValueType(),
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InsertSubreg->getOperand(i)), 0));
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Node->getOperand(i).getValueType(),
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Node->getOperand(i)), 0));
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}
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DAG.UpdateNodeOperands(InsertSubreg, Ops[0], Ops[1],
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InsertSubreg->getOperand(2));
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DAG.UpdateNodeOperands(Node, Ops);
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}
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/// \brief Fold the instructions after selecting them.
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@ -101,6 +101,7 @@ public:
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int32_t analyzeImmediate(const SDNode *N) const;
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SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const override;
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void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
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};
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} // End namespace llvm
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26
test/CodeGen/R600/copy-to-reg.ll
Normal file
26
test/CodeGen/R600/copy-to-reg.ll
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@ -0,0 +1,26 @@
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; RUN: llc -march=r600 -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs < %s
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; Test that CopyToReg instructions don't have non-register operands prior
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; to being emitted.
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; Make sure this doesn't crash
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; CHECK-LABEL: {{^}}copy_to_reg_frameindex:
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define void @copy_to_reg_frameindex(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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entry:
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%alloca = alloca [16 x i32]
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br label %loop
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loop:
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%inc = phi i32 [0, %entry], [%inc.i, %loop]
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%ptr = getelementptr [16 x i32]* %alloca, i32 0, i32 %inc
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store i32 %inc, i32* %ptr
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%inc.i = add i32 %inc, 1
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%cnd = icmp uge i32 %inc.i, 16
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br i1 %cnd, label %done, label %loop
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done:
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%tmp0 = getelementptr [16 x i32]* %alloca, i32 0, i32 0
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%tmp1 = load i32* %tmp0
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store i32 %tmp1, i32 addrspace(1)* %out
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ret void
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}
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