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InstCombine: Turn urem to bitwise-and more often
Use isKnownToBeAPowerOfTwo in visitUrem so that we may more aggressively fold away urem instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181661 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Majnemer
parent
d84ccfaf50
commit
a8ccefc0a3
@ -1027,31 +1027,13 @@ Instruction *InstCombiner::visitURem(BinaryOperator &I) {
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if (Instruction *common = commonIRemTransforms(I))
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return common;
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// X urem C^2 -> X and C-1
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{ const APInt *C;
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if (match(Op1, m_Power2(C)))
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return BinaryOperator::CreateAnd(Op0,
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ConstantInt::get(I.getType(), *C-1));
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}
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// Turn A % (C << N), where C is 2^k, into A & ((C << N)-1)
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if (match(Op1, m_Shl(m_Power2(), m_Value()))) {
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// X urem Y -> X and Y-1, where Y is a power of 2,
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if (isKnownToBeAPowerOfTwo(Op1, /*OrZero*/true)) {
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Constant *N1 = Constant::getAllOnesValue(I.getType());
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Value *Add = Builder->CreateAdd(Op1, N1);
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return BinaryOperator::CreateAnd(Op0, Add);
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}
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// urem X, (select Cond, 2^C1, 2^C2) -->
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// select Cond, (and X, C1-1), (and X, C2-1)
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// when C1&C2 are powers of two.
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{ Value *Cond; const APInt *C1, *C2;
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if (match(Op1, m_Select(m_Value(Cond), m_Power2(C1), m_Power2(C2)))) {
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Value *TrueAnd = Builder->CreateAnd(Op0, *C1-1, Op1->getName()+".t");
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Value *FalseAnd = Builder->CreateAnd(Op0, *C2-1, Op1->getName()+".f");
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return SelectInst::Create(Cond, TrueAnd, FalseAnd);
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}
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}
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// (zext A) urem (zext B) --> zext (A urem B)
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if (ZExtInst *ZOp0 = dyn_cast<ZExtInst>(Op0))
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if (Value *ZOp1 = dyn_castZExtVal(Op1, ZOp0->getSrcTy()))
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@ -1,36 +1,56 @@
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; This test makes sure that these instructions are properly eliminated.
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; This test makes sure that urem instructions are properly eliminated.
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;
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; RUN: opt < %s -instcombine -S | not grep rem
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; END.
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define i32 @test1(i32 %A) {
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; CHECK: @test1
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; CHECK-NEXT: ret i32 0
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%B = srem i32 %A, 1 ; ISA constant 0
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ret i32 %B
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}
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define i32 @test2(i32 %A) { ; 0 % X = 0, we don't need to preserve traps
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; CHECK: @test2
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; CHECK-NEXT: ret i32 0
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%B = srem i32 0, %A
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ret i32 %B
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}
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define i32 @test3(i32 %A) {
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; CHECK: @test3
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; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 7
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; CHECK-NEXT: ret i32 [[AND]]
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%B = urem i32 %A, 8
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ret i32 %B
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}
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define i1 @test3a(i32 %A) {
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; CHECK: @test3a
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; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 7
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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%B = srem i32 %A, -8
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%C = icmp ne i32 %B, 0
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ret i1 %C
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}
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define i32 @test4(i32 %X, i1 %C) {
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; CHECK: @test4
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; CHECK-NEXT: [[SEL:%.*]] = select i1 %C, i32 0, i32 7
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SEL]], %X
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%V = select i1 %C, i32 1, i32 8
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%R = urem i32 %X, %V
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ret i32 %R
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}
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define i32 @test5(i32 %X, i8 %B) {
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; CHECK: @test5
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 %B to i32
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; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 32, [[ZEXT]]
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; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], %X
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; CHECK-NEXT: ret i32 [[AND]]
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%shift.upgrd.1 = zext i8 %B to i32
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%Amt = shl i32 32, %shift.upgrd.1
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%V = urem i32 %X, %Amt
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@ -38,29 +58,39 @@ define i32 @test5(i32 %X, i8 %B) {
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}
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define i32 @test6(i32 %A) {
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; CHECK: @test6
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; CHECK-NEXT: ret i32 undef
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%B = srem i32 %A, 0 ;; undef
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ret i32 %B
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}
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define i32 @test7(i32 %A) {
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; CHECK: @test7
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; CHECK-NEXT: ret i32 0
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%B = mul i32 %A, 8
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%C = srem i32 %B, 4
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ret i32 %C
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}
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define i32 @test8(i32 %A) {
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; CHECK: @test8
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; CHECK-NEXT: ret i32 0
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%B = shl i32 %A, 4
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%C = srem i32 %B, 8
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ret i32 %C
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}
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define i32 @test9(i32 %A) {
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; CHECK: @test9
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; CHECK-NEXT: ret i32 0
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%B = mul i32 %A, 64
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%C = urem i32 %B, 32
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ret i32 %C
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}
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define i32 @test10(i8 %c) {
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; CHECK: @test10
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; CHECK-NEXT: ret i32 0
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%tmp.1 = zext i8 %c to i32
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%tmp.2 = mul i32 %tmp.1, 4
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%tmp.3 = sext i32 %tmp.2 to i64
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@ -70,6 +100,8 @@ define i32 @test10(i8 %c) {
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}
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define i32 @test11(i32 %i) {
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; CHECK: @test11
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; CHECK-NEXT: ret i32 0
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%tmp.1 = and i32 %i, -2
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%tmp.3 = mul i32 %tmp.1, 2
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%tmp.5 = urem i32 %tmp.3, 4
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@ -77,12 +109,29 @@ define i32 @test11(i32 %i) {
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}
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define i32 @test12(i32 %i) {
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; CHECK: @test12
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; CHECK-NEXT: ret i32 0
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%tmp.1 = and i32 %i, -4
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%tmp.5 = srem i32 %tmp.1, 2
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ret i32 %tmp.5
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}
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define i32 @test13(i32 %i) {
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; CHECK: @test13
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; CHECK-NEXT: ret i32 0
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%x = srem i32 %i, %i
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ret i32 %x
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}
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define i64 @test14(i64 %x, i32 %y) {
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; CHECK: @test14
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, %y
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[SHL]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add i64 [[ZEXT]], -1
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; CHECK-NEXT: [[AND:%.*]] = and i64 [[ADD]], %x
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; CHECK-NEXT: ret i64 [[AND]]
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%shl = shl i32 1, %y
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%zext = zext i32 %shl to i64
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%urem = urem i64 %x, %zext
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ret i64 %urem
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}
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