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updates for changes in nodes

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22808 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-16 21:58:15 +00:00
parent 707ebc5dd6
commit a8cd01524f
2 changed files with 21 additions and 19 deletions
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18
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -128,8 +128,8 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
if (!ArgLive) break; if (!ArgLive) break;
if (GPR_remaining > 0) { if (GPR_remaining > 0) {
MF.addLiveIn(GPR[GPR_idx]); MF.addLiveIn(GPR[GPR_idx]);
argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
DAG.getRoot()); GPR[GPR_idx], MVT::i32);
if (ObjectVT != MVT::i32) if (ObjectVT != MVT::i32)
argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot); argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
} else { } else {
@ -141,14 +141,14 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
if (GPR_remaining > 0) { if (GPR_remaining > 0) {
SDOperand argHi, argLo; SDOperand argHi, argLo;
MF.addLiveIn(GPR[GPR_idx]); MF.addLiveIn(GPR[GPR_idx]);
argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot()); argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
// If we have two or more remaining argument registers, then both halves // If we have two or more remaining argument registers, then both halves
// of the i64 can be sourced from there. Otherwise, the lower half will // of the i64 can be sourced from there. Otherwise, the lower half will
// have to come off the stack. This can happen when an i64 is preceded // have to come off the stack. This can happen when an i64 is preceded
// by 28 bytes of arguments. // by 28 bytes of arguments.
if (GPR_remaining > 1) { if (GPR_remaining > 1) {
MF.addLiveIn(GPR[GPR_idx+1]); MF.addLiveIn(GPR[GPR_idx+1]);
argLo = DAG.getCopyFromReg(GPR[GPR_idx+1], MVT::i32, argHi); argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32);
} else { } else {
int FI = MFI->CreateFixedObject(4, ArgOffset+4); int FI = MFI->CreateFixedObject(4, ArgOffset+4);
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
@ -168,8 +168,8 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
if (!ArgLive) break; if (!ArgLive) break;
if (FPR_remaining > 0) { if (FPR_remaining > 0) {
MF.addLiveIn(FPR[FPR_idx]); MF.addLiveIn(FPR[FPR_idx]);
argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT, argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
DAG.getRoot()); FPR[FPR_idx], ObjectVT);
--FPR_remaining; --FPR_remaining;
++FPR_idx; ++FPR_idx;
} else { } else {
@ -217,7 +217,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
std::vector<SDOperand> MemOps; std::vector<SDOperand> MemOps;
for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
MF.addLiveIn(GPR[GPR_idx]); MF.addLiveIn(GPR[GPR_idx]);
SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot()); SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
Val, FIN, DAG.getSrcValue(NULL)); Val, FIN, DAG.getSrcValue(NULL));
MemOps.push_back(Store); MemOps.push_back(Store);
@ -298,8 +298,8 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
// Set up a copy of the stack pointer for use loading and storing any // Set up a copy of the stack pointer for use loading and storing any
// arguments that may not fit in the registers available for argument // arguments that may not fit in the registers available for argument
// passing. // passing.
SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32, SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
DAG.getEntryNode()); PPC::R1, MVT::i32);
// Figure out which arguments are going to go in registers, and which in // Figure out which arguments are going to go in registers, and which in
// memory. Also, if this is a vararg function, floating point operations // memory. Also, if this is a vararg function, floating point operations

22
lib/Target/PowerPC/PPCISelPattern.cpp
View File

@ -808,11 +808,12 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
SDNode *Node = N.Val; SDNode *Node = N.Val;
MVT::ValueType DestType = N.getValueType(); MVT::ValueType DestType = N.getValueType();
if (Node->getOpcode() == ISD::CopyFromReg && if (Node->getOpcode() == ISD::CopyFromReg) {
(MRegisterInfo::isVirtualRegister(cast<RegSDNode>(Node)->getReg()) || unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
cast<RegSDNode>(Node)->getReg() == PPC::R1))
// Just use the specified register as our input. // Just use the specified register as our input.
return cast<RegSDNode>(Node)->getReg(); if (MRegisterInfo::isVirtualRegister(Reg) || Reg == PPC::R1)
return Reg;
}
unsigned &Reg = ExprMap[N]; unsigned &Reg = ExprMap[N];
if (Reg) return Reg; if (Reg) return Reg;
@ -1085,7 +1086,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
DestType = N.getValue(0).getValueType(); DestType = N.getValue(0).getValueType();
if (Result == 1) if (Result == 1)
Result = ExprMap[N.getValue(0)] = MakeReg(DestType); Result = ExprMap[N.getValue(0)] = MakeReg(DestType);
Tmp1 = dyn_cast<RegSDNode>(Node)->getReg(); Tmp1 = dyn_cast<RegisterSDNode>(Node->getOperand(1))->getReg();
if (MVT::isInteger(DestType)) if (MVT::isInteger(DestType))
BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1); BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
else else
@ -1877,12 +1878,12 @@ void ISel::Select(SDOperand N) {
return; return;
case ISD::CopyToReg: case ISD::CopyToReg:
Select(N.getOperand(0)); Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1)); Tmp1 = SelectExpr(N.getOperand(2));
Tmp2 = cast<RegSDNode>(N)->getReg(); Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
if (Tmp1 != Tmp2) { if (Tmp1 != Tmp2) {
if (N.getOperand(1).getValueType() == MVT::f64 || if (N.getOperand(2).getValueType() == MVT::f64 ||
N.getOperand(1).getValueType() == MVT::f32) N.getOperand(2).getValueType() == MVT::f32)
BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1); BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
else else
BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1); BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
@ -1890,7 +1891,8 @@ void ISel::Select(SDOperand N) {
return; return;
case ISD::ImplicitDef: case ISD::ImplicitDef:
Select(N.getOperand(0)); Select(N.getOperand(0));
BuildMI(BB, PPC::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg()); BuildMI(BB, PPC::IMPLICIT_DEF, 0,
cast<RegisterSDNode>(N.getOperand(1))->getReg());
return; return;
case ISD::RET: case ISD::RET:
switch (N.getNumOperands()) { switch (N.getNumOperands()) {