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https://github.com/c64scene-ar/llvm-6502.git
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Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides
eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen change. This unfortunately requires SystemZ to switch to the list-burr scheduler, in order to handle the physreg defs properly, however that's what LLVM has available at this time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85357 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
parent
04ea6e5150
commit
aa123224c4
@ -75,7 +75,13 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
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setStackPointerRegisterToSaveRestore(SystemZ::R15D);
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setSchedulingPreference(SchedulingForLatency);
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// TODO: It may be better to default to latency-oriented scheduling, however
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// LLVM's current latency-oriented scheduler can't handle physreg definitions
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// such as SystemZ has with PSW, so set this to the register-pressure
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// scheduler, because it can.
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setSchedulingPreference(SchedulingForRegPressure);
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setBooleanContents(ZeroOrOneBooleanContent);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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@ -663,7 +669,7 @@ SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
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DebugLoc dl = LHS.getDebugLoc();
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return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
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dl, MVT::Flag, LHS, RHS);
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dl, MVT::i64, LHS, RHS);
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}
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@ -25,15 +25,15 @@ def fpimmneg0 : PatLeaf<(fpimm), [{
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return N->isExactlyValue(-0.0);
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}]>;
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let usesCustomDAGSchedInserter = 1 in {
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let Uses = [PSW], usesCustomDAGSchedInserter = 1 in {
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def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
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"# SelectF32 PSEUDO",
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[(set FP32:$dst,
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(SystemZselect FP32:$src1, FP32:$src2, imm:$cc))]>;
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(SystemZselect FP32:$src1, FP32:$src2, imm:$cc, PSW))]>;
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def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
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"# SelectF64 PSEUDO",
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[(set FP64:$dst,
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(SystemZselect FP64:$src1, FP64:$src2, imm:$cc))]>;
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(SystemZselect FP64:$src1, FP64:$src2, imm:$cc, PSW))]>;
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}
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//===----------------------------------------------------------------------===//
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@ -32,12 +32,12 @@ def SDT_SystemZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
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def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
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def SDT_CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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def SDT_BrCond : SDTypeProfile<0, 2,
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def SDT_BrCond : SDTypeProfile<0, 3,
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[SDTCisVT<0, OtherVT>,
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SDTCisI8<1>]>;
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def SDT_SelectCC : SDTypeProfile<1, 3,
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SDTCisI8<1>, SDTCisVT<2, i64>]>;
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def SDT_SelectCC : SDTypeProfile<1, 4,
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[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
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SDTCisI8<3>]>;
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SDTCisI8<3>, SDTCisVT<4, i64>]>;
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def SDT_Address : SDTypeProfile<1, 1,
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[SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
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@ -54,11 +54,11 @@ def SystemZcallseq_start :
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def SystemZcallseq_end :
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SDNode<"ISD::CALLSEQ_END", SDT_SystemZCallSeqEnd,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
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def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
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def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest>;
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def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest>;
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def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
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[SDNPHasChain, SDNPInFlag]>;
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def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
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[SDNPHasChain]>;
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def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC>;
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def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
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@ -74,15 +74,15 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
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"#ADJCALLSTACKUP",
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[(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
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let usesCustomDAGSchedInserter = 1 in {
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let Uses = [PSW], usesCustomDAGSchedInserter = 1 in {
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def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
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"# Select32 PSEUDO",
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[(set GR32:$dst,
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(SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
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(SystemZselect GR32:$src1, GR32:$src2, imm:$cc, PSW))]>;
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def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
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"# Select64 PSEUDO",
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[(set GR64:$dst,
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(SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
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(SystemZselect GR64:$src1, GR64:$src2, imm:$cc, PSW))]>;
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}
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@ -106,46 +106,46 @@ let isBranch = 1, isTerminator = 1 in {
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let Uses = [PSW] in {
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def JO : Pseudo<(outs), (ins brtarget:$dst),
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"jo\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_O)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_O, PSW)]>;
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def JH : Pseudo<(outs), (ins brtarget:$dst),
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"jh\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_H, PSW)]>;
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def JNLE: Pseudo<(outs), (ins brtarget:$dst),
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"jnle\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE, PSW)]>;
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def JL : Pseudo<(outs), (ins brtarget:$dst),
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"jl\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_L, PSW)]>;
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def JNHE: Pseudo<(outs), (ins brtarget:$dst),
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"jnhe\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE, PSW)]>;
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def JLH : Pseudo<(outs), (ins brtarget:$dst),
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"jlh\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH, PSW)]>;
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def JNE : Pseudo<(outs), (ins brtarget:$dst),
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"jne\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE, PSW)]>;
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def JE : Pseudo<(outs), (ins brtarget:$dst),
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"je\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_E, PSW)]>;
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def JNLH: Pseudo<(outs), (ins brtarget:$dst),
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"jnlh\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH, PSW)]>;
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def JHE : Pseudo<(outs), (ins brtarget:$dst),
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"jhe\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE, PSW)]>;
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def JNL : Pseudo<(outs), (ins brtarget:$dst),
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"jnl\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL, PSW)]>;
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def JLE : Pseudo<(outs), (ins brtarget:$dst),
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"jle\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE, PSW)]>;
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def JNH : Pseudo<(outs), (ins brtarget:$dst),
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"jnh\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH, PSW)]>;
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def JNO : Pseudo<(outs), (ins brtarget:$dst),
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"jno\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO)]>;
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO, PSW)]>;
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} // Uses = [PSW]
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} // isBranch = 1
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