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Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides

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eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.

This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85357 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2009-10-28 00:55:57 +00:00
parent 04ea6e5150
commit aa123224c4
3 changed files with 36 additions and 30 deletions
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10
lib/Target/SystemZ/SystemZISelLowering.cpp
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@ -75,7 +75,13 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
setStackPointerRegisterToSaveRestore(SystemZ::R15D);
setSchedulingPreference(SchedulingForLatency);
// TODO: It may be better to default to latency-oriented scheduling, however
// LLVM's current latency-oriented scheduler can't handle physreg definitions
// such as SystemZ has with PSW, so set this to the register-pressure
// scheduler, because it can.
setSchedulingPreference(SchedulingForRegPressure);
setBooleanContents(ZeroOrOneBooleanContent);
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
@ -663,7 +669,7 @@ SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
DebugLoc dl = LHS.getDebugLoc();
return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
dl, MVT::Flag, LHS, RHS);
dl, MVT::i64, LHS, RHS);
}