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R600: Custom lower f32 = uint_to_fp i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193701 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -134,6 +134,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
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setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
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setOperationAction(ISD::MUL, MVT::i64, Expand);
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setOperationAction(ISD::UDIV, MVT::i32, Expand);
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@ -251,6 +253,7 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
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case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::STORE: return LowerSTORE(Op, DAG);
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case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
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case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
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}
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return Op;
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}
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@ -672,6 +675,25 @@ SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
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return DAG.getMergeValues(Ops, 2, DL);
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}
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SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
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SelectionDAG &DAG) const {
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SDValue S0 = Op.getOperand(0);
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SDLoc DL(Op);
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if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
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return SDValue();
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// f32 uint_to_fp i64
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SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
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DAG.getConstant(0, MVT::i32));
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SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
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SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
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DAG.getConstant(1, MVT::i32));
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SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
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FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
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DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
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return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
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}
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//===----------------------------------------------------------------------===//
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// Helper functions
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@ -37,6 +37,7 @@ private:
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/// \brief Split a vector store into multiple scalar stores.
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/// \returns The resulting chain.
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SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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protected:
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@ -1,10 +1,10 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
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; R600-CHECK: @uint_to_fp_v2i32
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; R600-CHECK-LABEL: @uint_to_fp_v2i32
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; R600-CHECK-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W
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; R600-CHECK-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X
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; SI-CHECK: @uint_to_fp_v2i32
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; SI-CHECK-LABEL: @uint_to_fp_v2i32
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; SI-CHECK: V_CVT_F32_U32_e32
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; SI-CHECK: V_CVT_F32_U32_e32
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define void @uint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) {
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@ -13,12 +13,12 @@ define void @uint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) {
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ret void
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}
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; R600-CHECK: @uint_to_fp_v4i32
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; R600-CHECK-LABEL: @uint_to_fp_v4i32
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; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI-CHECK: @uint_to_fp_v4i32
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; SI-CHECK-LABEL: @uint_to_fp_v4i32
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; SI-CHECK: V_CVT_F32_U32_e32
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; SI-CHECK: V_CVT_F32_U32_e32
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; SI-CHECK: V_CVT_F32_U32_e32
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@ -29,3 +29,18 @@ define void @uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspac
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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; R600-CHECK-LABEL: @uint_to_fp_i64_f32
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; R600-CHECK: UINT_TO_FLT
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; R600-CHECK: UINT_TO_FLT
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; R600-CHECK: MULADD_IEEE
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; SI-CHECK-LABEL: @uint_to_fp_i64_f32
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; SI-CHECK: V_CVT_F32_U32_e32
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; SI-CHECK: V_CVT_F32_U32_e32
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; SI-CHECK: V_MAD_F32
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define void @uint_to_fp_i64_f32(float addrspace(1)* %out, i64 %in) {
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entry:
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%0 = uitofp i64 %in to float
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store float %0, float addrspace(1)* %out
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ret void
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}
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