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Stop inferring isVariadic from instruction patterns.

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Instructions are now only marked as variadic if they use variable_ops in
their ins list.

A variadic SDNode is typically used for call nodes that have the call
arguments as operands.

A variadic MachineInstr can actually encode a variable number of
operands, for example ARM's stm/ldm instructions. A call instruction
does not have to be variadic. The call argument registers are added as
implicit operands.

This change remove the MCID::Variadic flags from most call and return
instructions, allowing us to better verify their operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162599 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-08-24 21:08:09 +00:00
parent 0745b649ed
commit aaaecfce70
1 changed files with 5 additions and 1 deletions
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6
utils/TableGen/CodeGenDAGPatterns.cpp
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@ -2502,7 +2502,11 @@ static bool InferFromPattern(CodeGenInstruction &InstInfo,
// These flags are silently added without any verification.
InstInfo.isBitcast |= PatInfo.isBitcast;
InstInfo.Operands.isVariadic |= PatInfo.isVariadic;
// Don't infer isVariadic. This flag means something different on SDNodes and
// instructions. For example, a CALL SDNode is variadic because it has the
// call arguments as operands, but a CALL instruction is not variadic - it
// has argument registers as implicit, not explicit uses.
return Error;
}