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FP_TO_INT*_IN_MEM and x87 FP Select support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25188 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
bb90a7aa7b
commit
aaca22ca91
@ -18,6 +18,7 @@
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#include "llvm/GlobalValue.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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@ -550,6 +551,63 @@ SDOperand X86DAGToDAGISel::Select(SDOperand N) {
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return CodeGenMap[N] = CurDAG->getTargetNode(Opc, VT, Result);
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break;
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}
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case X86ISD::FP_TO_INT16_IN_MEM:
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case X86ISD::FP_TO_INT32_IN_MEM:
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case X86ISD::FP_TO_INT64_IN_MEM: {
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assert(N.getOperand(1).getValueType() == MVT::f64);
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// Change the floating point control register to use "round towards zero"
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// mode when truncating to an integer value.
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MachineFunction &MF = CurDAG->getMachineFunction();
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int CWFI = MF.getFrameInfo()->CreateStackObject(2, 2);
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SDOperand CWSlot = CurDAG->getFrameIndex(CWFI, MVT::i32);
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SDOperand Base, Scale, Index, Disp;
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(void)SelectAddr(CWSlot, Base, Scale, Index, Disp);
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SDOperand Chain = N.getOperand(0);
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// Save the control word.
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Chain = CurDAG->getTargetNode(X86::FNSTCW16m, MVT::Other,
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Base, Scale, Index, Disp, Chain);
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// Load the old value of the high byte of the control word.
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SDOperand OldCW =
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CurDAG->getTargetNode(X86::MOV16rm, MVT::i16, MVT::Other,
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Base, Scale, Index, Disp, Chain);
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Chain = OldCW.getValue(1);
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// Set the high part to be round to zero...
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Chain = CurDAG->getTargetNode(X86::MOV16mi, MVT::Other,
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Base, Scale, Index, Disp,
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CurDAG->getConstant(0xC7F, MVT::i16),
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Chain);
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// Reload the modified control word now...
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Chain = CurDAG->getTargetNode(X86::FLDCW16m, MVT::Other,
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Base, Scale, Index, Disp, Chain);
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// Restore the memory image of control word to original value
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Chain = CurDAG->getTargetNode(X86::MOV16mr, MVT::Other,
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Base, Scale, Index, Disp, OldCW, Chain);
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switch (Opcode) {
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case X86ISD::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
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case X86ISD::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
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case X86ISD::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
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}
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SDOperand N1 = Select(N.getOperand(1));
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SDOperand Base2, Scale2, Index2, Disp2;
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(void)SelectAddr(N.getOperand(2), Base2, Scale2, Index2, Disp2);
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Chain = CurDAG->getTargetNode(Opc, MVT::Other,
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Base2, Scale2, Index2, Disp2, N1, Chain);
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// Reload the modified control word now...
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CodeGenMap[N] =
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Chain = CurDAG->getTargetNode(X86::FLDCW16m, MVT::Other,
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Base, Scale, Index, Disp, Chain);
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return Chain;
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}
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}
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return SelectCode(N);
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@ -1192,6 +1192,26 @@ static unsigned CCToX86CondCode(SDOperand CC, bool isFP) {
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return X86CC;
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}
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/// SupportedByFPCMOV - is there a floating point cmov for the specific
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/// X86 condition code.
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/// Current x86 isa includes the following FP cmov instructions:
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/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
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static bool SupportedByFPCMOV(unsigned X86CC) {
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switch (X86CC) {
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default:
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return false;
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case X86ISD::COND_B:
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case X86ISD::COND_BE:
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case X86ISD::COND_E:
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case X86ISD::COND_P:
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case X86ISD::COND_A:
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case X86ISD::COND_AE:
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case X86ISD::COND_NE:
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case X86ISD::COND_NP:
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return true;
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}
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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@ -1444,21 +1464,32 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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}
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}
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case ISD::SELECT: {
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SDOperand Cond = Op.getOperand(0);
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SDOperand CC;
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if (Cond.getOpcode() == X86ISD::SETCC) {
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CC = Cond.getOperand(0);
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Cond = Cond.getOperand(1);
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} else if (Cond.getOpcode() == ISD::SETCC) {
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CC = Cond.getOperand(2);
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bool isFP = MVT::isFloatingPoint(Cond.getOperand(1).getValueType());
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MVT::ValueType VT = Op.getValueType();
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bool isFP = MVT::isFloatingPoint(VT);
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bool isFPStack = isFP && (X86Vector < SSE2);
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bool isFPSSE = isFP && (X86Vector >= SSE2);
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bool isValid = false;
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SDOperand Op0 = Op.getOperand(0);
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SDOperand Cond, CC;
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if (Op0.getOpcode() == X86ISD::SETCC) {
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CC = Op0.getOperand(0);
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Cond = Op0.getOperand(1);
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isValid =
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!(isFPStack &&
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!SupportedByFPCMOV(cast<ConstantSDNode>(CC)->getSignExtended()));
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} else if (Op0.getOpcode() == ISD::SETCC) {
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CC = Op0.getOperand(2);
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bool isFP = MVT::isFloatingPoint(Op0.getOperand(1).getValueType());
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unsigned X86CC = CCToX86CondCode(CC, isFP);
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CC = DAG.getConstant(X86CC, MVT::i8);
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Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
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Cond.getOperand(0), Cond.getOperand(1));
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} else {
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Op0.getOperand(0), Op0.getOperand(1));
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isValid = true;
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}
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if (!isValid) {
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CC = DAG.getConstant(X86ISD::COND_E, MVT::i8);
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Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
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Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
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}
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std::vector<MVT::ValueType> Tys;
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@ -377,6 +377,13 @@ def IMPLICIT_DEF_R16 : I<0, Pseudo, (ops R16:$dst),
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def IMPLICIT_DEF_R32 : I<0, Pseudo, (ops R32:$dst),
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"#IMPLICIT_DEF $dst",
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[(set R32:$dst, (undef))]>;
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def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
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"#IMPLICIT_DEF $dst",
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[(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
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def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
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"#IMPLICIT_DEF $dst",
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[(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
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let isTerminator = 1 in
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let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
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@ -2687,14 +2694,30 @@ def FTST : FPI<0xE4, RawFrm, (ops), "ftst">, D9;
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// Floating point cmovs.
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let isTwoAddress = 1 in {
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def FpCMOVB : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>;
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def FpCMOVBE : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>;
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def FpCMOVE : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>;
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def FpCMOVP : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>;
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def FpCMOVAE : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>;
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def FpCMOVA : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>;
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def FpCMOVNE : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>;
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def FpCMOVNP : FpI<(ops RST:$dst, RFP:$src1, RFP:$src2), CondMovFP, []>;
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def FpCMOVB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
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[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
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X86_COND_B, STATUS))]>;
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def FpCMOVBE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
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[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
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X86_COND_BE, STATUS))]>;
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def FpCMOVE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
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[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
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X86_COND_E, STATUS))]>;
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def FpCMOVP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
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[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
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X86_COND_P, STATUS))]>;
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def FpCMOVAE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
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[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
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X86_COND_AE, STATUS))]>;
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def FpCMOVA : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
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[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
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X86_COND_A, STATUS))]>;
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def FpCMOVNE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
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[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
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X86_COND_NE, STATUS))]>;
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def FpCMOVNP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
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[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
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X86_COND_NP, STATUS))]>;
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}
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def FCMOVB : FPI<0xC0, AddRegFrm, (ops RST:$op),
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@ -2866,8 +2889,6 @@ def : Pat<(X86fst RFP:$src, addr:$op, f64), (FpST64m addr:$op, RFP:$src)>;
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def : Pat<(f64 fp64immneg0), (FpCHS (FpLD0))>, Requires<[FPStack]>;
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def : Pat<(f64 fp64immneg1), (FpCHS (FpLD1))>, Requires<[FPStack]>;
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// FR64 undef
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def : Pat<(f64 (undef)), (FLD0SD)>, Requires<[HasSSE2]>;
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// RFP undef
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def : Pat<(f64 (undef)), (FpLD0)>, Requires<[FPStack]>;
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