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ARM assembly parsing of MUL instruction.

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Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-07-20 18:20:31 +00:00
parent 0381c21d2d
commit ab40f4b737
2 changed files with 16 additions and 1 deletions
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3
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -1977,7 +1977,8 @@ StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
// First, split out any predication code. Ignore mnemonics we know aren't
// predicated but do have a carry-set and so weren't caught above.
if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs") {
if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
Mnemonic != "muls") {
unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
.Case("eq", ARMCC::EQ)
.Case("ne", ARMCC::NE)

14
test/MC/ARM/basic-arm-instructions.s
View File

@ -811,6 +811,20 @@ _func:
@ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1]
@ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1]
@------------------------------------------------------------------------------
@ MUL
@------------------------------------------------------------------------------
mul r5, r6, r7
muls r5, r6, r7
mulgt r5, r6, r7
mulsle r5, r6, r7
@ CHECK: mul r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xe0]
@ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0]
@ CHECK: mulgt r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xc0]
@ CHECK: mulsle r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xd0]
@------------------------------------------------------------------------------
@ STM*
@------------------------------------------------------------------------------