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Fix epilogue codegen to avoid leaving the stack pointer in an invalid
state. Previously Thumb2 would restore sp from fp like this: mov sp, r7 sub, sp, #4 If an interrupt is taken after the 'mov' but before the 'sub', callee-saved registers might be clobbered by the interrupt handler. Instead, try restoring directly from sp: add sp, #4 Or, if necessary (with VLA, etc.) use a scratch register to compute sp and then restore it: sub.w r4, r7, #8 mov sp, r7 rdar://8465407 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119977 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -694,10 +694,11 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Spill R4 if Thumb2 function requires stack realignment - it will be used as
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// scratch register.
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// scratch register. Also spill R4 if Thumb2 function has varsized objects,
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// since it's always posible to restore sp from fp in a single instruction.
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// FIXME: It will be better just to find spare register here.
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if (needsStackRealignment(MF) &&
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AFI->isThumb2Function())
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if (AFI->isThumb2Function() &&
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(MFI->hasVarSizedObjects() || needsStackRealignment(MF)))
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MF.getRegInfo().setPhysRegUsed(ARM::R4);
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// Spill LR if Thumb1 function uses variable length argument lists.
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@ -17,6 +17,7 @@
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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@ -212,15 +213,21 @@ void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
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if (NumBytes) {
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// Adjust SP after all the callee-save spills.
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
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if (HasFP)
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if (HasFP && isARM)
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// Restore from fp only in ARM mode: e.g. sub sp, r7, #24
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// Note it's not safe to do this in Thumb2 mode because it would have
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// taken two instructions:
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// mov sp, r7
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// sub sp, #24
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// If an interrupt is taken between the two instructions, then sp is in
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// an inconsistent state (pointing to the middle of callee-saved area).
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// The interrupt handler can end up clobbering the registers.
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AFI->setShouldRestoreSPFromFP(true);
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}
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if (STI.isTargetELF() && hasFP(MF)) {
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if (STI.isTargetELF() && hasFP(MF))
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MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
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AFI->getFramePtrSpillOffset());
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AFI->setShouldRestoreSPFromFP(true);
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}
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AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
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AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
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@ -275,7 +282,7 @@ void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
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// If the frame has variable sized objects then the epilogue must restore
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// the sp from fp.
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if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
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if (MFI->hasVarSizedObjects())
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AFI->setShouldRestoreSPFromFP(true);
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}
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@ -326,9 +333,21 @@ void ARMFrameInfo::emitEpilogue(MachineFunction &MF,
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if (isARM)
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emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
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ARMCC::AL, 0, TII);
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else
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emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
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else {
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// It's not possible to restore SP from FP in a single instruction.
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// For Darwin, this looks like:
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// mov sp, r7
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// sub sp, #24
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// This is bad, if an interrupt is taken after the mov, sp is in an
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// inconsistent state.
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// Use the first callee-saved register as a scratch register.
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assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
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"No scratch register to restore SP from FP!");
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emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
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ARMCC::AL, 0, TII);
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
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.addReg(ARM::R4);
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}
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} else {
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// Thumb2 or ARM.
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if (isARM)
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@ -17,6 +17,7 @@
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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@ -117,13 +118,6 @@ void Thumb1FrameInfo::emitPrologue(MachineFunction &MF) const {
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dl = MBBI->getDebugLoc();
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}
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// Adjust FP so it point to the stack slot that contains the previous FP.
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if (hasFP(MF)) {
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
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.addFrameIndex(FramePtrSpillFI).addImm(0);
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AFI->setShouldRestoreSPFromFP(true);
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}
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// Determine starting offsets of spill areas.
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unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
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unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
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@ -132,12 +126,21 @@ void Thumb1FrameInfo::emitPrologue(MachineFunction &MF) const {
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AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
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AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
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AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
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NumBytes = DPRCSOffset;
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if (NumBytes) {
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// Adjust FP so it point to the stack slot that contains the previous FP.
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if (hasFP(MF)) {
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
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.addFrameIndex(FramePtrSpillFI).addImm(0);
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if (NumBytes > 7)
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// If offset is > 7 then sp cannot be adjusted in a single instruction,
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// try restoring from fp instead.
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AFI->setShouldRestoreSPFromFP(true);
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}
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if (NumBytes)
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// Insert it after all the callee-save spills.
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emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes);
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}
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if (STI.isTargetELF() && hasFP(MF))
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MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
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@ -219,10 +222,14 @@ void Thumb1FrameInfo::emitEpilogue(MachineFunction &MF,
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NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
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// Reset SP based on frame pointer only if the stack frame extends beyond
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// frame pointer stack slot or target is ELF and the function has FP.
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if (NumBytes)
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emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
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if (NumBytes) {
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assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
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"No scratch register to restore SP from FP!");
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emitThumbRegPlusImmediate(MBB, MBBI, ARM::R4, FramePtr, -NumBytes,
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TII, *RegInfo, dl);
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else
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
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.addReg(ARM::R4);
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} else
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
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.addReg(FramePtr);
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} else {
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@ -1,7 +1,7 @@
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; RUN: llc < %s -march=arm
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; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | count 1
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; RUN: llc < %s -mtriple=arm-linux-gnu --disable-fp-elim | \
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; RUN: grep mov | count 3
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; RUN: grep mov | count 2
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; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 2
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@str = internal constant [12 x i8] c"Hello World\00"
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@ -1,12 +1,15 @@
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; RUN: llc < %s -march=thumb | not grep {ldr sp}
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; RUN: llc < %s -mtriple=thumb-apple-darwin | \
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; RUN: not grep {sub.*r7}
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; RUN: llc < %s -march=thumb | grep {mov.*r6, sp}
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; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
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%struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
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%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
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define void @t1(%struct.state* %v) {
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; CHECK: t1:
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; CHECK: push
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; CHECK: add r7, sp, #12
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; CHECK: mov r2, sp
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; CHECK: subs r4, r2, r1
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; CHECK: mov sp, r4
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%tmp6 = load i32* null
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%tmp8 = alloca float, i32 %tmp6
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store i32 1, i32* null
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@ -34,6 +37,18 @@ declare fastcc void @f2(float*, float*, float*, i32)
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@str215 = external global [2 x i8]
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define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) {
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; CHECK: t2:
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; CHECK: push
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; CHECK: add r7, sp, #12
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; CHECK: sub sp, #8
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; CHECK: mov r6, sp
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; CHECK: str r2, [r6, #4]
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; CHECK: str r0, [r6]
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; CHECK-NOT: ldr r0, [sp
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; CHECK: ldr r0, [r6, #4]
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; CHECK: mov r0, sp
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; CHECK: subs r5, r0, r1
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; CHECK: mov sp, r5
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%tmp1 = call i32 @strlen( i8* %tag )
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%tmp3 = call i32 @strlen( i8* %contents )
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%tmp4 = add i32 %tmp1, 2
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@ -12,8 +12,8 @@ define void @test2() {
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; CHECK: test2:
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; CHECK: ldr r0, LCPI
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; CHECK: add sp, r0
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; CHECK: mov sp, r7
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; CHECK: sub sp, #4
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; CHECK: subs r4, r7, #4
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; CHECK: mov sp, r4
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%tmp = alloca [ 4168 x i8 ] , align 4
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ret void
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}
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@ -24,8 +24,8 @@ define i32 @test3() {
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; CHECK: add sp, r2
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; CHECK: ldr r1, LCPI
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; CHECK: add r1, sp
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; CHECK: mov sp, r7
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; CHECK: sub sp, #4
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; CHECK: subs r4, r7, #4
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; CHECK: mov sp, r4
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%retval = alloca i32, align 4
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%tmp = alloca i32, align 4
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%a = alloca [805306369 x i8], align 16
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@ -5,8 +5,13 @@
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define hidden i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind {
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entry:
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; CHECK: __gcov_execlp:
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; CHECK: mov sp, r7
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; CHECK: sub sp, #4
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; CHECK: sub sp, #8
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; CHECK: push
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; CHECK: add r7, sp, #4
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; CHECK: subs r4, r7, #4
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; CHECK: mov sp, r4
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; CHECK-NOT: mov sp, r7
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; CHECK: add sp, #8
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call void @__gcov_flush() nounwind
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br i1 undef, label %bb5, label %bb
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define internal fastcc i32 @Callee(i32 %i) nounwind {
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entry:
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; CHECK: Callee:
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; CHECK: push
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; CHECK: mov r4, sp
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; CHECK: sub.w r12, r4, #1000
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; CHECK: mov sp, r12
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%0 = icmp eq i32 %i, 0 ; <i1> [#uses=1]
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br i1 %0, label %bb2, label %bb
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@ -17,9 +21,11 @@ bb: ; preds = %entry
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ret i32 %4
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bb2: ; preds = %entry
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; Must restore sp from fp here
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; CHECK: mov sp, r7
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; CHECK: sub sp, #8
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; Must restore sp from fp here. Make sure not to leave sp in a temporarily invalid
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; state though. rdar://8465407
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; CHECK-NOT: mov sp, r7
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; CHECK: sub.w r4, r7, #8
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; CHECK: mov sp, r4
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; CHECK: pop
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ret i32 0
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}
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34
test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
Normal file
34
test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
Normal file
@ -0,0 +1,34 @@
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; rdar://8465407
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
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%struct.buf = type opaque
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declare void @bar() nounwind optsize
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define void @foo() nounwind optsize {
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; CHECK: foo:
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; CHECK: push
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; CHECK: add r7, sp, #4
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; CHECK: sub sp, #4
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entry:
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%m.i = alloca %struct.buf*, align 4
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br label %bb
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bb:
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br i1 undef, label %bb3, label %bb2
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bb2:
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call void @bar() nounwind optsize
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br i1 undef, label %bb, label %bb3
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bb3:
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br i1 undef, label %return, label %bb
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return:
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; CHECK: %return
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; 'mov sp, r7' would have left sp in an invalid state
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; CHECK-NOT: mov sp, r7
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; CHECK-NOT: sub, sp, #4
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; CHECK: add sp, #4
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ret void
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}
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