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state. Previously Thumb2 would restore sp from fp like this: mov sp, r7 sub, sp, #4 If an interrupt is taken after the 'mov' but before the 'sub', callee-saved registers might be clobbered by the interrupt handler. Instead, try restoring directly from sp: add sp, #4 Or, if necessary (with VLA, etc.) use a scratch register to compute sp and then restore it: sub.w r4, r7, #8 mov sp, r7 rdar://8465407 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119977 91177308-0d34-0410-b5e6-96231b3b80d8
495 lines
19 KiB
C++
495 lines
19 KiB
C++
//=======- ARMFrameInfo.cpp - ARM Frame Information ------------*- C++ -*-====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of TargetFrameInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMFrameInfo.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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/// hasFP - Return true if the specified function should have a dedicated frame
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/// pointer register. This is true if the function has variable sized allocas
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/// or if frame pointer elimination is disabled.
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///
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bool ARMFrameInfo::hasFP(const MachineFunction &MF) const {
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const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
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// Mac OS X requires FP not to be clobbered for backtracing purpose.
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if (STI.isTargetDarwin())
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return true;
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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// Always eliminate non-leaf frame pointers.
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return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
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RegInfo->needsStackRealignment(MF) ||
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MFI->hasVarSizedObjects() ||
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MFI->isFrameAddressTaken());
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}
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// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
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// not required, we reserve argument space for call sites in the function
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// immediately on entry to the current function. This eliminates the need for
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// add/sub sp brackets around call sites. Returns true if the call frame is
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// included as part of the stack frame.
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bool ARMFrameInfo::hasReservedCallFrame(const MachineFunction &MF) const {
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const MachineFrameInfo *FFI = MF.getFrameInfo();
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unsigned CFSize = FFI->getMaxCallFrameSize();
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// It's not always a good idea to include the call frame as part of the
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// stack frame. ARM (especially Thumb) has small immediate offset to
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// address the stack frame. So a large call frame can cause poor codegen
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// and may even makes it impossible to scavenge a register.
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if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
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return false;
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return !MF.getFrameInfo()->hasVarSizedObjects();
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}
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// canSimplifyCallFramePseudos - If there is a reserved call frame, the
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// call frame pseudos can be simplified. Unlike most targets, having a FP
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// is not sufficient here since we still may reference some objects via SP
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// even when FP is available in Thumb2 mode.
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bool ARMFrameInfo::canSimplifyCallFramePseudos(const MachineFunction &MF)const {
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return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
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}
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static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
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for (unsigned i = 0; CSRegs[i]; ++i)
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if (Reg == CSRegs[i])
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return true;
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return false;
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}
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static bool isCSRestore(MachineInstr *MI,
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const ARMBaseInstrInfo &TII,
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const unsigned *CSRegs) {
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// Integer spill area is handled with "pop".
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if (MI->getOpcode() == ARM::LDMIA_RET ||
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MI->getOpcode() == ARM::t2LDMIA_RET ||
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MI->getOpcode() == ARM::LDMIA_UPD ||
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MI->getOpcode() == ARM::t2LDMIA_UPD ||
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MI->getOpcode() == ARM::VLDMDIA_UPD) {
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// The first two operands are predicates. The last two are
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// imp-def and imp-use of SP. Check everything in between.
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for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
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if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
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return false;
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return true;
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}
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return false;
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}
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static void
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emitSPUpdate(bool isARM,
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MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
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DebugLoc dl, const ARMBaseInstrInfo &TII,
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int NumBytes,
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ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
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if (isARM)
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emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
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Pred, PredReg, TII);
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else
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emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
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Pred, PredReg, TII);
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}
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void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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const ARMBaseRegisterInfo *RegInfo =
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static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const ARMBaseInstrInfo &TII =
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*static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
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assert(!AFI->isThumb1OnlyFunction() &&
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"This emitPrologue does not support Thumb1!");
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bool isARM = !AFI->isThumbFunction();
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unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
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unsigned NumBytes = MFI->getStackSize();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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unsigned FramePtr = RegInfo->getFrameRegister(MF);
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// Determine the sizes of each callee-save spill areas and record which frame
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// belongs to which callee-save spill areas.
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unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
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int FramePtrSpillFI = 0;
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// Allocate the vararg register save area. This is not counted in NumBytes.
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if (VARegSaveSize)
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
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if (!AFI->hasStackFrame()) {
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if (NumBytes != 0)
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
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return;
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}
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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int FI = CSI[i].getFrameIdx();
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switch (Reg) {
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case ARM::R4:
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case ARM::R5:
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case ARM::R6:
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case ARM::R7:
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case ARM::LR:
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if (Reg == FramePtr)
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FramePtrSpillFI = FI;
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AFI->addGPRCalleeSavedArea1Frame(FI);
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GPRCS1Size += 4;
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break;
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case ARM::R8:
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case ARM::R9:
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case ARM::R10:
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case ARM::R11:
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if (Reg == FramePtr)
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FramePtrSpillFI = FI;
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if (STI.isTargetDarwin()) {
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AFI->addGPRCalleeSavedArea2Frame(FI);
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GPRCS2Size += 4;
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} else {
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AFI->addGPRCalleeSavedArea1Frame(FI);
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GPRCS1Size += 4;
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}
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break;
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default:
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AFI->addDPRCalleeSavedAreaFrame(FI);
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DPRCSSize += 8;
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}
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}
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// Move past area 1.
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if (GPRCS1Size > 0) MBBI++;
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// Set FP to point to the stack slot that contains the previous FP.
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// For Darwin, FP is R7, which has now been stored in spill area 1.
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// Otherwise, if this is not Darwin, all the callee-saved registers go
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// into spill area 1, including the FP in R11. In either case, it is
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// now safe to emit this assignment.
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bool HasFP = hasFP(MF);
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if (HasFP) {
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unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
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.addFrameIndex(FramePtrSpillFI).addImm(0);
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AddDefaultCC(AddDefaultPred(MIB));
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}
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// Move past area 2.
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if (GPRCS2Size > 0) MBBI++;
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// Determine starting offsets of spill areas.
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unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
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unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
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unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
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if (HasFP)
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AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
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NumBytes);
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AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
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AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
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AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
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// Move past area 3.
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if (DPRCSSize > 0) MBBI++;
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NumBytes = DPRCSOffset;
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if (NumBytes) {
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// Adjust SP after all the callee-save spills.
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
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if (HasFP && isARM)
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// Restore from fp only in ARM mode: e.g. sub sp, r7, #24
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// Note it's not safe to do this in Thumb2 mode because it would have
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// taken two instructions:
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// mov sp, r7
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// sub sp, #24
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// If an interrupt is taken between the two instructions, then sp is in
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// an inconsistent state (pointing to the middle of callee-saved area).
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// The interrupt handler can end up clobbering the registers.
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AFI->setShouldRestoreSPFromFP(true);
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}
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if (STI.isTargetELF() && hasFP(MF))
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MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
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AFI->getFramePtrSpillOffset());
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AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
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AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
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AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
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// If we need dynamic stack realignment, do it here. Be paranoid and make
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// sure if we also have VLAs, we have a base pointer for frame access.
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if (RegInfo->needsStackRealignment(MF)) {
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unsigned MaxAlign = MFI->getMaxAlignment();
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assert (!AFI->isThumb1OnlyFunction());
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if (!AFI->isThumbFunction()) {
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// Emit bic sp, sp, MaxAlign
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AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
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TII.get(ARM::BICri), ARM::SP)
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.addReg(ARM::SP, RegState::Kill)
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.addImm(MaxAlign-1)));
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} else {
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// We cannot use sp as source/dest register here, thus we're emitting the
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// following sequence:
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// mov r4, sp
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// bic r4, r4, MaxAlign
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// mov sp, r4
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// FIXME: It will be better just to find spare register here.
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
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.addReg(ARM::SP, RegState::Kill);
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AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
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TII.get(ARM::t2BICri), ARM::R4)
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.addReg(ARM::R4, RegState::Kill)
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.addImm(MaxAlign-1)));
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
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.addReg(ARM::R4, RegState::Kill);
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}
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AFI->setShouldRestoreSPFromFP(true);
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}
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// If we need a base pointer, set it up here. It's whatever the value
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// of the stack pointer is at this point. Any variable size objects
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// will be allocated after this, so we can still use the base pointer
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// to reference locals.
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if (RegInfo->hasBasePointer(MF)) {
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if (isARM)
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BuildMI(MBB, MBBI, dl,
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TII.get(ARM::MOVr), RegInfo->getBaseRegister())
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.addReg(ARM::SP)
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.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
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else
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BuildMI(MBB, MBBI, dl,
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TII.get(ARM::tMOVgpr2gpr), RegInfo->getBaseRegister())
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.addReg(ARM::SP);
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}
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// If the frame has variable sized objects then the epilogue must restore
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// the sp from fp.
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if (MFI->hasVarSizedObjects())
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AFI->setShouldRestoreSPFromFP(true);
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}
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void ARMFrameInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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assert(MBBI->getDesc().isReturn() &&
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"Can only insert epilog into returning blocks");
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unsigned RetOpcode = MBBI->getOpcode();
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DebugLoc dl = MBBI->getDebugLoc();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
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const ARMBaseInstrInfo &TII =
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*static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
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assert(!AFI->isThumb1OnlyFunction() &&
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"This emitEpilogue does not support Thumb1!");
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bool isARM = !AFI->isThumbFunction();
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unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
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int NumBytes = (int)MFI->getStackSize();
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unsigned FramePtr = RegInfo->getFrameRegister(MF);
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if (!AFI->hasStackFrame()) {
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if (NumBytes != 0)
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
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} else {
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// Unwind MBBI to point to first LDR / VLDRD.
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const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
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if (MBBI != MBB.begin()) {
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do
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--MBBI;
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while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
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if (!isCSRestore(MBBI, TII, CSRegs))
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++MBBI;
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}
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// Move SP to start of FP callee save spill area.
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NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
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AFI->getGPRCalleeSavedArea2Size() +
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AFI->getDPRCalleeSavedAreaSize());
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// Reset SP based on frame pointer only if the stack frame extends beyond
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// frame pointer stack slot or target is ELF and the function has FP.
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if (AFI->shouldRestoreSPFromFP()) {
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NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
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if (NumBytes) {
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if (isARM)
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emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
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ARMCC::AL, 0, TII);
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else {
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// It's not possible to restore SP from FP in a single instruction.
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// For Darwin, this looks like:
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// mov sp, r7
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// sub sp, #24
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// This is bad, if an interrupt is taken after the mov, sp is in an
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// inconsistent state.
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// Use the first callee-saved register as a scratch register.
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assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
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"No scratch register to restore SP from FP!");
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emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
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ARMCC::AL, 0, TII);
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
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.addReg(ARM::R4);
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}
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} else {
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// Thumb2 or ARM.
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if (isARM)
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BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
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.addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
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else
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
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.addReg(FramePtr);
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}
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} else if (NumBytes)
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
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// Increment past our save areas.
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if (AFI->getDPRCalleeSavedAreaSize()) MBBI++;
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if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
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if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
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}
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if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
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RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
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// Tail call return: adjust the stack pointer and jump to callee.
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MBBI = prior(MBB.end());
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MachineOperand &JumpTarget = MBBI->getOperand(0);
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// Jump to label or value in register.
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if (RetOpcode == ARM::TCRETURNdi) {
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BuildMI(MBB, MBBI, dl,
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TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
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addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
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JumpTarget.getTargetFlags());
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} else if (RetOpcode == ARM::TCRETURNdiND) {
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BuildMI(MBB, MBBI, dl,
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TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
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addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
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JumpTarget.getTargetFlags());
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} else if (RetOpcode == ARM::TCRETURNri) {
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BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
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addReg(JumpTarget.getReg(), RegState::Kill);
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} else if (RetOpcode == ARM::TCRETURNriND) {
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BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
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addReg(JumpTarget.getReg(), RegState::Kill);
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}
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MachineInstr *NewMI = prior(MBBI);
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for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
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NewMI->addOperand(MBBI->getOperand(i));
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// Delete the pseudo instruction TCRETURN.
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MBB.erase(MBBI);
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}
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if (VARegSaveSize)
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
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}
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// Provide a base+offset reference to an FI slot for debug info. It's the
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// same as what we use for resolving the code-gen references for now.
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// FIXME: This can go wrong when references are SP-relative and simple call
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// frames aren't used.
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int
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ARMFrameInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
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unsigned &FrameReg) const {
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return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
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}
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int
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ARMFrameInfo::ResolveFrameIndexReference(const MachineFunction &MF,
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int FI,
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unsigned &FrameReg,
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int SPAdj) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const ARMBaseRegisterInfo *RegInfo =
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static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
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int FPOffset = Offset - AFI->getFramePtrSpillOffset();
|
|
bool isFixed = MFI->isFixedObjectIndex(FI);
|
|
|
|
FrameReg = ARM::SP;
|
|
Offset += SPAdj;
|
|
if (AFI->isGPRCalleeSavedArea1Frame(FI))
|
|
return Offset - AFI->getGPRCalleeSavedArea1Offset();
|
|
else if (AFI->isGPRCalleeSavedArea2Frame(FI))
|
|
return Offset - AFI->getGPRCalleeSavedArea2Offset();
|
|
else if (AFI->isDPRCalleeSavedAreaFrame(FI))
|
|
return Offset - AFI->getDPRCalleeSavedAreaOffset();
|
|
|
|
// When dynamically realigning the stack, use the frame pointer for
|
|
// parameters, and the stack/base pointer for locals.
|
|
if (RegInfo->needsStackRealignment(MF)) {
|
|
assert (hasFP(MF) && "dynamic stack realignment without a FP!");
|
|
if (isFixed) {
|
|
FrameReg = RegInfo->getFrameRegister(MF);
|
|
Offset = FPOffset;
|
|
} else if (MFI->hasVarSizedObjects()) {
|
|
assert(RegInfo->hasBasePointer(MF) &&
|
|
"VLAs and dynamic stack alignment, but missing base pointer!");
|
|
FrameReg = RegInfo->getBaseRegister();
|
|
}
|
|
return Offset;
|
|
}
|
|
|
|
// If there is a frame pointer, use it when we can.
|
|
if (hasFP(MF) && AFI->hasStackFrame()) {
|
|
// Use frame pointer to reference fixed objects. Use it for locals if
|
|
// there are VLAs (and thus the SP isn't reliable as a base).
|
|
if (isFixed || (MFI->hasVarSizedObjects() && !RegInfo->hasBasePointer(MF))) {
|
|
FrameReg = RegInfo->getFrameRegister(MF);
|
|
return FPOffset;
|
|
} else if (MFI->hasVarSizedObjects()) {
|
|
assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
|
|
// Try to use the frame pointer if we can, else use the base pointer
|
|
// since it's available. This is handy for the emergency spill slot, in
|
|
// particular.
|
|
if (AFI->isThumb2Function()) {
|
|
if (FPOffset >= -255 && FPOffset < 0) {
|
|
FrameReg = RegInfo->getFrameRegister(MF);
|
|
return FPOffset;
|
|
}
|
|
} else
|
|
FrameReg = RegInfo->getBaseRegister();
|
|
} else if (AFI->isThumb2Function()) {
|
|
// In Thumb2 mode, the negative offset is very limited. Try to avoid
|
|
// out of range references.
|
|
if (FPOffset >= -255 && FPOffset < 0) {
|
|
FrameReg = RegInfo->getFrameRegister(MF);
|
|
return FPOffset;
|
|
}
|
|
} else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
|
|
// Otherwise, use SP or FP, whichever is closer to the stack slot.
|
|
FrameReg = RegInfo->getFrameRegister(MF);
|
|
return FPOffset;
|
|
}
|
|
}
|
|
// Use the base pointer if we have one.
|
|
if (RegInfo->hasBasePointer(MF))
|
|
FrameReg = RegInfo->getBaseRegister();
|
|
return Offset;
|
|
}
|
|
|
|
int ARMFrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
|
|
unsigned FrameReg;
|
|
return getFrameIndexReference(MF, FI, FrameReg);
|
|
}
|