mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Coalesce insert_subreg undef, x first to avoid phase ordering issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91103 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
64bdde2093
commit
ac94863a1c
@ -745,8 +745,16 @@ unsigned LiveIntervals::getVNInfoSourceReg(const VNInfo *VNI) const {
|
||||
if (VNI->getCopy()->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
|
||||
// If it's extracting out of a physical register, return the sub-register.
|
||||
unsigned Reg = VNI->getCopy()->getOperand(1).getReg();
|
||||
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
||||
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
||||
unsigned SrcSubReg = VNI->getCopy()->getOperand(2).getImm();
|
||||
unsigned DstSubReg = VNI->getCopy()->getOperand(0).getSubReg();
|
||||
if (SrcSubReg == DstSubReg)
|
||||
// %reg1034:3<def> = EXTRACT_SUBREG %EDX, 3
|
||||
// reg1034 can still be coalesced to EDX.
|
||||
return Reg;
|
||||
assert(DstSubReg == 0);
|
||||
Reg = tri_->getSubReg(Reg, VNI->getCopy()->getOperand(2).getImm());
|
||||
}
|
||||
return Reg;
|
||||
} else if (VNI->getCopy()->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
|
||||
VNI->getCopy()->getOpcode() == TargetInstrInfo::SUBREG_TO_REG)
|
||||
|
@ -2422,9 +2422,15 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
|
||||
|
||||
// If this isn't a copy nor a extract_subreg, we can't join intervals.
|
||||
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
|
||||
bool isInsUndef = false;
|
||||
if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
|
||||
DstReg = Inst->getOperand(0).getReg();
|
||||
SrcReg = Inst->getOperand(1).getReg();
|
||||
} else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
|
||||
DstReg = Inst->getOperand(0).getReg();
|
||||
SrcReg = Inst->getOperand(2).getReg();
|
||||
if (Inst->getOperand(1).isUndef())
|
||||
isInsUndef = true;
|
||||
} else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
|
||||
Inst->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
|
||||
DstReg = Inst->getOperand(0).getReg();
|
||||
@ -2434,7 +2440,8 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
|
||||
|
||||
bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
|
||||
bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
|
||||
if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
|
||||
if (isInsUndef ||
|
||||
(li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()))
|
||||
ImpDefCopies.push_back(CopyRec(Inst, 0));
|
||||
else if (SrcIsPhys || DstIsPhys)
|
||||
PhysCopies.push_back(CopyRec(Inst, 0));
|
||||
@ -2442,9 +2449,9 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
|
||||
VirtCopies.push_back(CopyRec(Inst, 0));
|
||||
}
|
||||
|
||||
// Try coalescing implicit copies first, followed by copies to / from
|
||||
// physical registers, then finally copies from virtual registers to
|
||||
// virtual registers.
|
||||
// Try coalescing implicit copies and insert_subreg <undef> first,
|
||||
// followed by copies to / from physical registers, then finally copies
|
||||
// from virtual registers to virtual registers.
|
||||
for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
|
||||
CopyRec &TheCopy = ImpDefCopies[i];
|
||||
bool Again = false;
|
||||
|
Loading…
Reference in New Issue
Block a user