6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

Typo

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71975 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-05-17 10:15:22 +00:00
parent 48839d9973
commit aceb620de8
3 changed files with 18 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -468,7 +468,7 @@ SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
}
while (ShiftAmount--)
Victim = DAG.getNode((Opc == ISD::SRA ? MSP430ISD::RRA : MSP430ISD::RLA),
Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
dl, VT, Victim);
return Victim;

4
lib/Target/MSP430/MSP430InstrInfo.td
View File

@ -624,12 +624,12 @@ def SHL16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
(implicit SRW)]>;
def SAR8r1c : Pseudo<(outs GR8:$dst), (ins GR8:$src),
"clrc\n"
"clrc\n\t"
"rrc.b\t$dst",
[(set GR8:$dst, (MSP430rrc GR8:$src)),
(implicit SRW)]>;
def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src),
"clrc\n"
"clrc\n\t"
"rrc.w\t$dst",
[(set GR16:$dst, (MSP430rrc GR16:$src)),
(implicit SRW)]>;

15
test/CodeGen/MSP430/2009-05-17-Shift.ll Normal file
View File

@ -0,0 +1,15 @@
; RUN: llvm-as < %s | llc -march=msp430 | grep rra | count 1
define i16 @lsr2u16(i16 %x.arg) nounwind {
%retval = alloca i16
%x = alloca i16
store i16 %x.arg, i16* %x
%1 = load i16* %x
%2 = lshr i16 %1, 2
store i16 %2, i16* %retval
br label %return
return:
%3 = load i16* %retval
ret i16 %3
}