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Make this readable for newbies and those who can only understand one set of
grammar rules for the English language. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21503 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -137,7 +137,7 @@ classes, ensuring that it is portable.
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code generator and the set of reusable components that can be used to build
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target-specific backends. The two most important interfaces (<a
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href="#targetmachine"><tt>TargetMachine</tt></a> and <a
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href="#targetdata"><tt>TargetData</tt></a> classes) are the only ones that are
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href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
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required to be defined for a backend to fit into the LLVM system, but the others
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must be defined if the reusable code generator components are going to be
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used.</p>
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@ -188,30 +188,31 @@ set, then makes use of virtual registers in SSA form and physical registers that
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represent any required register assignments due to target constraints or calling
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conventions.</li>
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<li><b>SSA-based Machine Code Optimizations</b> - This (optional) stage consists
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of a series of machine-code optimizations that operate on the SSA-form produced
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by the instruction selector. Optimizations like modulo-scheduling, normal
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scheduling, or peephole optimization work here.</li>
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<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
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optional stage consists of a series of machine-code optimizations that
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operate on the SSA-form produced by the instruction selector. Optimizations
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like modulo-scheduling, normal scheduling, or peephole optimization work here.
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</li>
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<li><b>Register Allocation</b> - The target code is transformed from an infinite
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virtual register file in SSA form to the concrete register file used by the
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target. This phase introduces spill code and eliminates all virtual register
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references from the program.</li>
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<li><b><a name="#regalloc">Register Allocation</a></b> - The
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target code is transformed from an infinite virtual register file in SSA form
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to the concrete register file used by the target. This phase introduces spill
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code and eliminates all virtual register references from the program.</li>
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<li><b>Prolog/Epilog Code Insertion</b> - Once the machine code has been
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generated for the function and the amount of stack space required is known (used
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for LLVM alloca's and spill slots), the prolog and epilog code for the function
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can be inserted and "abstract stack location references" can be eliminated.
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This stage is responsible for implementing optimizations like frame-pointer
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elimination and stack packing.</li>
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<li><b><a name="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
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machine code has been generated for the function and the amount of stack space
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required is known (used for LLVM alloca's and spill slots), the prolog and
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epilog code for the function can be inserted and "abstract stack location
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references" can be eliminated. This stage is responsible for implementing
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optimizations like frame-pointer elimination and stack packing.</li>
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<li><b>Late Machine Code Optimizations</b> - Optimizations that operate on
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"final" machine code can go here, such as spill code scheduling and peephole
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optimizations.</li>
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<li><b><a name="latemco">Late Machine Code Optimizations</a></b> - Optimizations
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that operate on "final" machine code can go here, such as spill code scheduling
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and peephole optimizations.</li>
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<li><b>Code Emission</b> - The final stage actually outputs the code for
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the current function, either in the target assembler format or in machine
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code.</li>
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<li><b><a name="codemission">Code Emission</a></b> - The final stage actually
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puts out the code for the current function, either in the target assembler
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format or in machine code.</li>
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</ol>
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@ -245,11 +246,13 @@ targets with unusual requirements can be supported with custom passes as needed.
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<p>The target description classes require a detailed description of the target
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architecture. These target descriptions often have a large amount of common
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information (e.g., an add instruction is almost identical to a sub instruction).
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information (e.g., an <tt>add</tt> instruction is almost identical to a
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<tt>sub</tt> instruction).
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In order to allow the maximum amount of commonality to be factored out, the LLVM
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code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
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describe big chunks of the target machine, which allows the use of domain- and
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target-specific abstractions to reduce the amount of repetition.
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describe big chunks of the target machine, which allows the use of
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domain-specific and target-specific abstractions to reduce the amount of
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repetition.
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</p>
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</div>
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@ -264,11 +267,11 @@ target-specific abstractions to reduce the amount of repetition.
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<p>The LLVM target description classes (which are located in the
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<tt>include/llvm/Target</tt> directory) provide an abstract description of the
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target machine, independent of any particular client. These classes are
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designed to capture the <i>abstract</i> properties of the target (such as what
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instruction and registers it has), and do not incorporate any particular pieces
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of code generation algorithms (these interfaces do not take interference graphs
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as inputs or other algorithm-specific data structures).</p>
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target machine; independent of any particular client. These classes are
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designed to capture the <i>abstract</i> properties of the target (such as the
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instructions and registers it has), and do not incorporate any particular pieces
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of code generation algorithms. These interfaces do not take interference graphs
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as inputs or other algorithm-specific data structures.</p>
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<p>All of the target description classes (except the <tt><a
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href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
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@ -288,8 +291,9 @@ should be implemented by the target.</p>
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<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
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access the target-specific implementations of the various target description
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classes (with the <tt>getInstrInfo</tt>, <tt>getRegisterInfo</tt>,
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<tt>getFrameInfo</tt>, ... methods). This class is designed to be specialized by
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classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
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<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
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designed to be specialized by
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a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
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implements the various virtual methods. The only required target description
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class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
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@ -307,10 +311,11 @@ implemented as well.</p>
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<div class="doc_text">
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<p>The <tt>TargetData</tt> class is the only required target description class,
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and it is the only class that is not extensible (it cannot be derived from). It
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specifies information about how the target lays out memory for structures, the
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alignment requirements for various data types, the size of pointers in the
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target, and whether the target is little- or big-endian.</p>
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and it is the only class that is not extensible. You cannot derived a new
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class from it. <tt>TargetData</tt> specifies information about how the target
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lays out memory for structures, the alignment requirements for various data
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types, the size of pointers in the target, and whether the target is
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little-endian or big-endian.</p>
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</div>
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@ -323,10 +328,12 @@ target, and whether the target is little- or big-endian.</p>
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<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
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selectors primarily to describe how LLVM code should be lowered to SelectionDAG
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operations. Among other things, this class indicates an initial register class
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to use for various ValueTypes, which operations are natively supported by the
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target machine, and some other miscellaneous properties (such as the return type
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of setcc operations, the type to use for shift amounts, etc).</p>
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operations. Among other things, this class indicates:
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<ul><li>an initial register class to use for various ValueTypes,</li>
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<li>which operations are natively supported by the target machine,</li>
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<li>the return type of setcc operations, and</li>
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<li>the type to use for shift amounts, etc</li>.
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</ol></p>
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</div>
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@ -415,12 +422,12 @@ representation for machine code, as well as a register allocated, non-SSA form.
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<p>Target machine instructions are represented as instances of the
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<tt>MachineInstr</tt> class. This class is an extremely abstract way of
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representing machine instructions. In particular, all it keeps track of is
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an opcode number and some number of operands.</p>
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representing machine instructions. In particular, it only keeps track of
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an opcode number and a set of operands.</p>
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<p>The opcode number is an simple unsigned number that only has meaning to a
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<p>The opcode number is a simple unsigned number that only has meaning to a
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specific backend. All of the instructions for a target should be defined in
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the <tt>*InstrInfo.td</tt> file for the target, and the opcode enum values
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the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
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are auto-generated from this description. The <tt>MachineInstr</tt> class does
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not have any information about how to interpret the instruction (i.e., what the
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semantics of the instruction are): for that you must refer to the
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@ -439,9 +446,9 @@ and stores the result into the "%i3" register. In the LLVM code generator,
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the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
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first.</p>
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<p>Keeping destination operands at the beginning of the operand list has several
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advantages. In particular, the debugging printer will print the instruction
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like this:</p>
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<p>Keeping destination (definition) operands at the beginning of the operand
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list has several advantages. In particular, the debugging printer will print
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the instruction like this:</p>
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<pre>
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%r3 = add %i1, %i2
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@ -490,17 +497,18 @@ instructions. Usage of the <tt>BuildMI</tt> functions look like this:
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<p>
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The key thing to remember with the <tt>BuildMI</tt> functions is that you have
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to specify the number of operands that the machine instruction will take
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(allowing efficient memory allocation). Also, if operands default to be uses
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of values, not definitions. If you need to add a definition operand (other
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than the optional destination register), you must explicitly mark it as such.
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to specify the number of operands that the machine instruction will take. This
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allows for efficient memory allocation. You also need to specify if operands
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default to be uses of values, not definitions. If you need to add a definition
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operand (other than the optional destination register), you must explicitly
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mark it as such.
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</p>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection">
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<a name="fixedregs">Fixed (aka preassigned) registers</a>
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<a name="fixedregs">Fixed (preassigned) registers</a>
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</div>
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<div class="doc_text">
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@ -509,7 +517,7 @@ than the optional destination register), you must explicitly mark it as such.
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presence of fixed registers. In particular, there are often places in the
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instruction stream where the register allocator <em>must</em> arrange for a
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particular value to be in a particular register. This can occur due to
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limitations in the instruction set (e.g., the X86 can only do a 32-bit divide
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limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
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with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
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conventions. In any case, the instruction selector should emit code that
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copies a virtual register into or out of a physical register when needed.</p>
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@ -570,7 +578,7 @@ register.</p>
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<div class="doc_text">
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<p><tt>MachineInstr</tt>'s are initially instruction selected in SSA-form, and
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<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
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are maintained in SSA-form until register allocation happens. For the most
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part, this is trivially simple since LLVM is already in SSA form: LLVM PHI nodes
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become machine code PHI nodes, and virtual registers are only allowed to have a
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@ -602,7 +610,7 @@ explains how they work and some of the rationale behind their design.</p>
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<div class="doc_text">
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<p>
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Instruction Selection is the process of translating the LLVM code input to the
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Instruction Selection is the process of translating LLVM code presented to the
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code generator into target-specific machine instructions. There are several
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well-known ways to do this in the literature. In LLVM there are two main forms:
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the old-style 'simple' instruction selector (which effectively peephole selects
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@ -619,8 +627,9 @@ new port, we recommend that you write the instruction selector using the
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SelectionDAG infrastructure.</p>
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<p>In time, most of the target-specific code for instruction selection will be
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auto-generated from the target .td files. For now, however, the <a
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href="#selectiondag_select">Select Phase</a> must still be written by hand.</p>
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auto-generated from the target description (<tt>*.td</tt>) files. For now,
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however, the <a href="#selectiondag_select">Select Phase</a> must still be
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written by hand.</p>
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</div>
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<!-- _______________________________________________________________________ -->
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@ -631,39 +640,40 @@ href="#selectiondag_select">Select Phase</a> must still be written by hand.</p>
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<div class="doc_text">
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<p>
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The SelectionDAG provides an abstraction for representing code in a way that is
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amenable to instruction selection using automatic techniques
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(e.g. dynamic-programming based optimal pattern matching selectors), as well as
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an abstraction that is useful for other phases of code generation (in
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particular, instruction scheduling). Additionally, the SelectionDAG provides a
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host representation where a large variety of very-low-level (but
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target-independent) <a href="#selectiondag_optimize">optimizations</a> may be
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The SelectionDAG provides an abstraction for code representation in a way that
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is amenable to instruction selection using automatic techniques
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(e.g. dynamic-programming based optimal pattern matching selectors), It is also
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well suited to other phases of code generation; in particular, instruction scheduling. Additionally, the SelectionDAG provides a host representation where a
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large variety of very-low-level (but target-independent)
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<a href="#selectiondag_optimize">optimizations</a> may be
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performed: ones which require extensive information about the instructions
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efficiently supported by the target.
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</p>
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<p>
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The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
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<tt>SDNode</tt> class. The primary payload of the Node is its operation code
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(Opcode) that indicates what the operation the node performs. The various
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operation node types are described at the top of the
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<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file. Depending on the operation, nodes may contain additional information (e.g. the condition code
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<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
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operation code (Opcode) that indicates what operation the node performs.
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The various operation node types are described at the top of the
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<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file. Depending on the
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operation, nodes may contain additional information (e.g. the condition code
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for a SETCC node) contained in a derived class.</p>
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<p>Each node in the graph may define multiple values
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(e.g. for a combined div/rem operation and many other situations), though most
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operations define a single value. Each node also has some number of operands,
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which are edges to the node defining the used value. Because nodes may define
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multiple values, edges are represented by instances of the <tt>SDOperand</tt>
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class, which is a <SDNode, unsigned> pair, indicating the node and result
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value being used. Each value produced by a SDNode has an associated
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MVT::ValueType, indicating what type the value is.
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<p>Although most operations define a single value, each node in the graph may
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define multiple values. For example, a combined div/rem operation will define
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both the dividend and the remainder. Many other situations require multiple
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values as well. Each node also has some number of operands, which are edges
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to the node defining the used value. Because nodes may define multiple values,
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edges are represented by instances of the <tt>SDOperand</tt> class, which is
|
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a <SDNode, unsigned> pair, indicating the node and result
|
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value being used, respectively. Each value produced by an SDNode has an
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associated MVT::ValueType, indicating what type the value is.
|
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</p>
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<p>
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SelectionDAGs contain two different kinds of value: those that represent data
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SelectionDAGs contain two different kinds of values: those that represent data
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flow and those that represent control flow dependencies. Data values are simple
|
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edges with a integer or floating point value type. Control edges are
|
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edges with an integer or floating point value type. Control edges are
|
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represented as "chain" edges which are of type MVT::Other. These edges provide
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an ordering between nodes that have side effects (such as
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loads/stores/calls/return/etc). All nodes that have side effects should take a
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@ -673,23 +683,23 @@ value produced by an operation.</p>
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<p>
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A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
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always a marker node with Opcode of ISD::TokenFactor. The Root node is the
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final side effecting node in the token chain (for example, in a single basic
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block function, this would be the return node).
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always a marker node with an Opcode of ISD::TokenFactor. The Root node is the
|
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final side-effecting node in the token chain. For example, in a single basic
|
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block function, this would be the return node.
|
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</p>
|
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|
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<p>
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One important concept for SelectionDAGs is the notion of a "legal" vs "illegal"
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One important concept for SelectionDAGs is the notion of a "legal" vs. "illegal"
|
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DAG. A legal DAG for a target is one that only uses supported operations and
|
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supported types. On PowerPC, for example, a DAG with any values of i1, i8, i16,
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or i64 type would be illegal. The <a href="#selectiondag_legalize">legalize</a>
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phase is the one responsible for turning an illegal DAG into a legal DAG.
|
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phase is responsible for turning an illegal DAG into a legal DAG.
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</p>
|
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</div>
|
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection">
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<a name="selectiondag_process">SelectionDAG Code Generation Process</a>
|
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<a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
|
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</div>
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<div class="doc_text">
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@ -706,7 +716,7 @@ SelectionDAG-based instruction selection consists of the following steps:
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performs simple optimizations on the SelectionDAG to simplify it and
|
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recognize meta instructions (like rotates and div/rem pairs) for
|
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targets that support these meta operations. This makes the resultant code
|
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more efficient and the 'select' phase more simple.
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more efficient and the 'select instructions from DAG' phase (below) simpler.
|
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</li>
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<li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
|
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converts the illegal SelectionDAG to a legal SelectionDAG, by eliminating
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@ -734,11 +744,11 @@ rest of the code generation passes are run.</p>
|
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|
||||
<p>
|
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The initial SelectionDAG is naively peephole expanded from the LLVM input by
|
||||
the SelectionDAGLowering class in the SelectionDAGISel.cpp file. The idea of
|
||||
doing this pass is to expose as much low-level target-specific details to the
|
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SelectionDAG as possible. This pass is mostly hard-coded (e.g. an LLVM add
|
||||
turns into a SDNode add, a geteelementptr is expanded into the obvious
|
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arithmetic, etc) but does require target-specific hooks to lower calls and
|
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the <tt>SelectionDAGLowering</tt> class in the SelectionDAGISel.cpp file. The
|
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intent of this pass is to expose as much low-level, target-specific details
|
||||
to the SelectionDAG as possible. This pass is mostly hard-coded (e.g. an LLVM
|
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add turns into an SDNode add while a geteelementptr is expanded into the obvious
|
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arithmetic). This pass requires target-specific hooks to lower calls and
|
||||
returns, varargs, etc. For these features, the TargetLowering interface is
|
||||
used.
|
||||
</p>
|
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@ -759,10 +769,11 @@ tasks:</p>
|
||||
<ol>
|
||||
<li><p>Convert values of unsupported types to values of supported types.</p>
|
||||
<p>There are two main ways of doing this: promoting a small type to a larger
|
||||
type (e.g. f32 -> f64, or i16 -> i32), and expanding larger integer types
|
||||
type (e.g. f32 -> f64, or i16 -> i32), and demoting larg integer types
|
||||
to smaller ones (e.g. implementing i64 with i32 operations where
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possible). Promotion insert sign and zero extensions as needed to make
|
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sure that the final code has the same behavior as the input.</p>
|
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possible). Type conversions can insert sign and zero extensions as
|
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needed to make sure that the final code has the same behavior as the
|
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input.</p>
|
||||
</li>
|
||||
|
||||
<li><p>Eliminate operations that are not supported by the target in a supported
|
||||
@ -772,19 +783,20 @@ tasks:</p>
|
||||
conditional moves). Legalize takes care of either open-coding another
|
||||
sequence of operations to emulate the operation (this is known as
|
||||
expansion), promoting to a larger type that supports the operation
|
||||
(promotion), or can use a target-specific hook to implement the
|
||||
(promotion), or using a target-specific hook to implement the
|
||||
legalization.</p>
|
||||
</li>
|
||||
</ol>
|
||||
|
||||
<p>
|
||||
Instead of using a Legalize pass, we could require that every target-specific
|
||||
<a href="#selectiondag_optimize">selector</a> support and expand every operator
|
||||
and type even if they are not supported and may require many instructions to
|
||||
implement (in fact, this is the approach taken by the "simple" selectors).
|
||||
However, using a Legalize pass allows all of the cannonicalization patterns to
|
||||
be shared across targets, and makes it very easy to optimize the cannonicalized
|
||||
code (because it is still in the form of a DAG).
|
||||
<a href="#selectiondag_optimize">selector</a> supports and expands every
|
||||
operator and type even if they are not supported and may require many
|
||||
instructions to implement (in fact, this is the approach taken by the
|
||||
"simple" selectors). However, using a Legalize pass allows all of the
|
||||
cannonicalization patterns to be shared across targets which makes it very
|
||||
easy to optimize the cannonicalized code because it is still in the form of
|
||||
a DAG.
|
||||
</p>
|
||||
|
||||
</div>
|
||||
@ -798,11 +810,12 @@ code (because it is still in the form of a DAG).
|
||||
|
||||
<p>
|
||||
The SelectionDAG optimization phase is run twice for code generation: once
|
||||
immediately after the DAG is built and once after legalization. The first pass
|
||||
allows the initial code to be cleaned up, (for example) performing optimizations
|
||||
that depend on knowing that the operators have restricted type inputs. The second
|
||||
pass cleans up the messy code generated by the Legalize pass, allowing Legalize to
|
||||
be very simple (not having to take into account many special cases.
|
||||
immediately after the DAG is built and once after legalization. The first run
|
||||
of the pass allows the initial code to be cleaned up (e.g. performing
|
||||
optimizations that depend on knowing that the operators have restricted type
|
||||
inputs). The second run of the pass cleans up the messy code generated by the
|
||||
Legalize pass, allowing Legalize to be very simple since it can ignore many
|
||||
special cases.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
@ -838,8 +851,8 @@ International Conference on Compiler Construction (CC) 2004
|
||||
<p>The Select phase is the bulk of the target-specific code for instruction
|
||||
selection. This phase takes a legal SelectionDAG as input, and does simple
|
||||
pattern matching on the DAG to generate code. In time, the Select phase will
|
||||
be automatically generated from the targets InstrInfo.td file, which is why we
|
||||
want to make the Select phase a simple and mechanical as possible.</p>
|
||||
be automatically generated from the target's InstrInfo.td file, which is why we
|
||||
want to make the Select phase as simple and mechanical as possible.</p>
|
||||
|
||||
</div>
|
||||
|
||||
@ -853,13 +866,39 @@ want to make the Select phase a simple and mechanical as possible.</p>
|
||||
<ol>
|
||||
<li>Optional whole-function selection.</li>
|
||||
<li>Select is a graph translation phase.</li>
|
||||
<li>Place the machine instrs resulting from Select according to register pressure or a schedule.</li>
|
||||
<li>Place the machine instructions resulting from Select according to register
|
||||
pressure or a schedule.</li>
|
||||
<li>DAG Scheduling.</li>
|
||||
<li>Auto-generate the Select phase from the target .td files.</li>
|
||||
<li>Auto-generate the Select phase from the target description (*.td) files.
|
||||
</li>
|
||||
</ol>
|
||||
|
||||
</div>
|
||||
|
||||
|
||||
<!-- ======================================================================= -->
|
||||
<div class="doc_subsection">
|
||||
<a name="ssamco">SSA-based Machine Code Optimizations</a>
|
||||
</div>
|
||||
<div class="doc_text"><p>To Be Written</p></div>
|
||||
<!-- ======================================================================= -->
|
||||
<div class="doc_subsection">
|
||||
<a name="regalloc">Register Allocation</a>
|
||||
</div>
|
||||
<div class="doc_text"><p>To Be Written</p></div>
|
||||
<!-- ======================================================================= -->
|
||||
<div class="doc_subsection">
|
||||
<a name="proepicode">Prolog/Epilog Code Insertion</a>
|
||||
</div>
|
||||
<div class="doc_text"><p>To Be Written</p></div>
|
||||
<!-- ======================================================================= -->
|
||||
<div class="doc_subsection">
|
||||
<a name="latemco">Late Machine Code Optimizations</a>
|
||||
</div>
|
||||
<div class="doc_text"><p>To Be Written</p></div>
|
||||
<!-- ======================================================================= -->
|
||||
<div class="doc_subsection">
|
||||
<a name="codemission">Code Emission</a>
|
||||
</div>
|
||||
|
||||
<!-- *********************************************************************** -->
|
||||
<div class="doc_section">
|
||||
@ -869,7 +908,7 @@ want to make the Select phase a simple and mechanical as possible.</p>
|
||||
|
||||
<div class="doc_text">
|
||||
|
||||
<p>This section of the document explains any features or design decisions that
|
||||
<p>This section of the document explains features or design decisions that
|
||||
are specific to the code generator for a particular target.</p>
|
||||
|
||||
</div>
|
||||
@ -917,8 +956,8 @@ Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
|
||||
OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
|
||||
</pre>
|
||||
|
||||
<p>Stores and all other instructions treat the four memory operands in the same
|
||||
way, in the same order.</p>
|
||||
<p>Stores, and all other instructions, treat the four memory operands in the
|
||||
same way, in the same order.</p>
|
||||
|
||||
</div>
|
||||
|
||||
@ -930,9 +969,8 @@ way, in the same order.</p>
|
||||
<div class="doc_text">
|
||||
|
||||
<p>
|
||||
An instruction name consists of the base name, a default operand size
|
||||
followed by a character per operand with an optional special size. For
|
||||
example:</p>
|
||||
An instruction name consists of the base name, a default operand size, and a
|
||||
a character per operand with an optional special size. For example:</p>
|
||||
|
||||
<p>
|
||||
<tt>ADD8rr</tt> -> add, 8-bit register, 8-bit register<br>
|
||||
|
Loading…
Reference in New Issue
Block a user