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Teach two-address pass to update the "source" map so it doesn't perform a

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non-profitable commute using outdated info. The test case would still fail
because of poor pre-RA schedule. That will be fixed by MI scheduler.

rdar://11472010


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157038 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2012-05-18 01:33:51 +00:00
parent 6f55e3d57d
commit ad75364815
2 changed files with 23 additions and 1 deletions
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8
lib/CodeGen/TwoAddressInstructionPass.cpp
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@ -1521,6 +1521,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
#endif
// Emit a copy or rematerialize the definition.
bool isCopy = false;
const TargetRegisterClass *rc = MRI->getRegClass(regB);
MachineInstr *DefMI = MRI->getVRegDef(regB);
// If it's safe and profitable, remat the definition instead of
@ -1537,10 +1538,11 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
} else {
BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY),
regA).addReg(regB);
isCopy = true;
}
MachineBasicBlock::iterator prevMI = prior(mi);
// Update DistanceMap.
MachineBasicBlock::iterator prevMI = prior(mi);
DistanceMap.insert(std::make_pair(prevMI, Dist));
DistanceMap[mi] = ++Dist;
@ -1554,6 +1556,10 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
RemovedKillFlag = true;
}
MO.setReg(regA);
if (isCopy)
// Propagate SrcRegMap.
SrcRegMap[regA] = regB;
}
if (AllUsesCopied) {

16
test/CodeGen/X86/2012-05-17-TwoAddressBug.ll Normal file
View File

@ -0,0 +1,16 @@
; RUN: llc < %s -mtriple=x86_64-apple-macosx -pre-RA-sched=source | FileCheck %s
; Teach two-address pass to update the "source" map so it doesn't perform a
; non-profitable commute using outdated info. The test case would still fail
; because of poor pre-RA schedule. That will be fixed by MI scheduler.
; rdar://11472010
define i32 @t(i32 %mask) nounwind readnone ssp {
entry:
; CHECK: t:
; CHECK-NOT: mov
%sub = add i32 %mask, -65535
%shr = lshr i32 %sub, 23
%and = and i32 %mask, 1
%add = add i32 %shr, %and
ret i32 %add
}