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Fix null reference creation in ScheduleDAGInstrs constructor call.

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Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI
constructor call. It is undefined behavior to take references to these values.

This bug is reported by UBSan.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216118 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alexey Samsonov 2014-08-20 19:36:05 +00:00
parent 4b1cddbaf0
commit ada5f2a2c7
6 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/CodeGen/MachineScheduler.h
View File

@ -250,7 +250,7 @@ protected:
public:
ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
bool IsPostRA)
: ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, IsPostRA,
: ScheduleDAGInstrs(*C->MF, C->MLI, C->MDT, IsPostRA,
/*RemoveKillFlags=*/IsPostRA, C->LIS),
AA(C->AA), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), CurrentTop(),
CurrentBottom(), NextClusterPred(nullptr), NextClusterSucc(nullptr) {

8
include/llvm/CodeGen/ScheduleDAGInstrs.h
View File

@ -75,8 +75,8 @@ namespace llvm {
/// MachineInstrs.
class ScheduleDAGInstrs : public ScheduleDAG {
protected:
const MachineLoopInfo &MLI;
const MachineDominatorTree &MDT;
const MachineLoopInfo *MLI;
const MachineDominatorTree *MDT;
const MachineFrameInfo *MFI;
/// Live Intervals provides reaching defs in preRA scheduling.
@ -154,8 +154,8 @@ namespace llvm {
public:
explicit ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo &mli,
const MachineDominatorTree &mdt,
const MachineLoopInfo *mli,
const MachineDominatorTree *mdt,
bool IsPostRAFlag,
bool RemoveKillFlags = false,
LiveIntervals *LIS = nullptr);

2
lib/CodeGen/DFAPacketizer.cpp
View File

@ -115,7 +115,7 @@ public:
DefaultVLIWScheduler::DefaultVLIWScheduler(
MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
bool IsPostRA) :
ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) {
ScheduleDAGInstrs(MF, &MLI, &MDT, IsPostRA) {
CanHandleTerminators = true;
}

2
lib/CodeGen/PostRASchedulerList.cpp
View File

@ -197,7 +197,7 @@ SchedulePostRATDList::SchedulePostRATDList(
AliasAnalysis *AA, const RegisterClassInfo &RCI,
TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs)
: ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), AA(AA), EndIndex(0) {
: ScheduleDAGInstrs(MF, &MLI, &MDT, /*IsPostRA=*/true), AA(AA), EndIndex(0) {
const TargetMachine &TM = MF.getTarget();
const InstrItineraryData *InstrItins =

4
lib/CodeGen/ScheduleDAGInstrs.cpp
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@ -50,8 +50,8 @@ static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
cl::init(true), cl::desc("Enable use of TBAA during MI GAD construction"));
ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo &mli,
const MachineDominatorTree &mdt,
const MachineLoopInfo *mli,
const MachineDominatorTree *mdt,
bool IsPostRAFlag,
bool RemoveKillFlags,
LiveIntervals *lis)

2
lib/Target/Hexagon/HexagonMachineScheduler.cpp
View File

@ -145,7 +145,7 @@ void VLIWMachineScheduler::schedule() {
<< "********** MI Converging Scheduling VLIW BB#" << BB->getNumber()
<< " " << BB->getName()
<< " in_func " << BB->getParent()->getFunction()->getName()
<< " at loop depth " << MLI.getLoopDepth(BB)
<< " at loop depth " << MLI->getLoopDepth(BB)
<< " \n");
buildDAGWithRegPressure();