6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-19 06:31:18 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: Use InstFlag for VOP3 modifier operands

Browse Source 
InstFlag has a default value of 0 and will simplify the VOP3 patterns.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179829 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-04-19 02:11:00 +00:00
parent 3abd23bac5
commit ae2a8929d8
2 changed files with 14 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/R600/SIInstrInfo.td
View File

@ -259,14 +259,14 @@ multiclass VOPC_64 <bits<8> op, string opName,
class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 < class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
op, (outs VReg_32:$dst), op, (outs VReg_32:$dst),
(ins VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2, (ins VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2,
i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg), InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
>, VOP <opName>; >, VOP <opName>;
class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 < class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
op, (outs VReg_64:$dst), op, (outs VReg_64:$dst),
(ins VSrc_64:$src0, VSrc_64:$src1, VSrc_64:$src2, (ins VSrc_64:$src0, VSrc_64:$src1, VSrc_64:$src2,
i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg), InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
>, VOP <opName>; >, VOP <opName>;

25
lib/Target/R600/SIInstructions.td
View File

@ -990,17 +990,17 @@ def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
def : Pat < def : Pat <
(mul VSrc_32:$src0, VReg_32:$src1), (mul VSrc_32:$src0, VReg_32:$src1),
(V_MUL_LO_I32 VSrc_32:$src0, VReg_32:$src1, (i32 0), 0, 0, 0, 0) (V_MUL_LO_I32 VSrc_32:$src0, VReg_32:$src1, (i32 0))
>; >;
def : Pat < def : Pat <
(mulhu VSrc_32:$src0, VReg_32:$src1), (mulhu VSrc_32:$src0, VReg_32:$src1),
(V_MUL_HI_U32 VSrc_32:$src0, VReg_32:$src1, (i32 0), 0, 0, 0, 0) (V_MUL_HI_U32 VSrc_32:$src0, VReg_32:$src1, (i32 0))
>; >;
def : Pat < def : Pat <
(mulhs VSrc_32:$src0, VReg_32:$src1), (mulhs VSrc_32:$src0, VReg_32:$src1),
(V_MUL_HI_I32 VSrc_32:$src0, VReg_32:$src1, (i32 0), 0, 0, 0, 0) (V_MUL_HI_I32 VSrc_32:$src0, VReg_32:$src1, (i32 0))
>; >;
def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
@ -1475,20 +1475,20 @@ def : Pat <
(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
(V_CUBETC_F32 (EXTRACT_SUBREG VReg_128:$src, sub0), (V_CUBETC_F32 (EXTRACT_SUBREG VReg_128:$src, sub0),
(EXTRACT_SUBREG VReg_128:$src, sub1), (EXTRACT_SUBREG VReg_128:$src, sub1),
(EXTRACT_SUBREG VReg_128:$src, sub2), (EXTRACT_SUBREG VReg_128:$src, sub2)),
0, 0, 0, 0), sub0), sub0),
(V_CUBESC_F32 (EXTRACT_SUBREG VReg_128:$src, sub0), (V_CUBESC_F32 (EXTRACT_SUBREG VReg_128:$src, sub0),
(EXTRACT_SUBREG VReg_128:$src, sub1), (EXTRACT_SUBREG VReg_128:$src, sub1),
(EXTRACT_SUBREG VReg_128:$src, sub2), (EXTRACT_SUBREG VReg_128:$src, sub2)),
0, 0, 0, 0), sub1), sub1),
(V_CUBEMA_F32 (EXTRACT_SUBREG VReg_128:$src, sub0), (V_CUBEMA_F32 (EXTRACT_SUBREG VReg_128:$src, sub0),
(EXTRACT_SUBREG VReg_128:$src, sub1), (EXTRACT_SUBREG VReg_128:$src, sub1),
(EXTRACT_SUBREG VReg_128:$src, sub2), (EXTRACT_SUBREG VReg_128:$src, sub2)),
0, 0, 0, 0), sub2), sub2),
(V_CUBEID_F32 (EXTRACT_SUBREG VReg_128:$src, sub0), (V_CUBEID_F32 (EXTRACT_SUBREG VReg_128:$src, sub0),
(EXTRACT_SUBREG VReg_128:$src, sub1), (EXTRACT_SUBREG VReg_128:$src, sub1),
(EXTRACT_SUBREG VReg_128:$src, sub2), (EXTRACT_SUBREG VReg_128:$src, sub2)),
0, 0, 0, 0), sub3) sub3)
>; >;
def : Pat < def : Pat <
@ -1527,8 +1527,7 @@ def : Pat <
/********** ================== **********/ /********** ================== **********/
def : Pat <(f32 (fadd (fmul VSrc_32:$src0, VSrc_32:$src1), VSrc_32:$src2)), def : Pat <(f32 (fadd (fmul VSrc_32:$src0, VSrc_32:$src1), VSrc_32:$src2)),
(V_MAD_F32 VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2, (V_MAD_F32 VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2)>;
0, 0, 0, 0)>;
/********** ================== **********/ /********** ================== **********/
/********** SMRD Patterns **********/ /********** SMRD Patterns **********/