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https://github.com/c64scene-ar/llvm-6502.git
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Add bunch of branch folding stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76055 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
27766b548f
commit
ae46db85a9
@ -39,7 +39,8 @@ namespace llvm {
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NL = 10,
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LE = 11,
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NH = 12,
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NO = 13
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NO = 13,
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INVALID = -1
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};
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}
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@ -309,6 +309,137 @@ SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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return true;
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}
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bool SystemZInstrInfo::
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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assert(Cond.size() == 1 && "Invalid Xbranch condition!");
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SystemZCC::CondCodes CC = static_cast<SystemZCC::CondCodes>(Cond[0].getImm());
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Cond[0].setImm(getOppositeCondition(CC));
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return false;
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}
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bool SystemZInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB)const{
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if (MBB.empty()) return false;
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switch (MBB.back().getOpcode()) {
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case SystemZ::RET: // Return.
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case SystemZ::JMP: // Uncond branch.
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case SystemZ::JMPr: // Indirect branch.
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return true;
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default: return false;
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}
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}
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bool SystemZInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.isTerminator()) return false;
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// Conditional branch is a special case.
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if (TID.isBranch() && !TID.isBarrier())
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return true;
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if (!TID.isPredicable())
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return true;
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return !isPredicated(MI);
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}
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bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// Start from the bottom of the block and work up, examining the
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// terminator instructions.
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MachineBasicBlock::iterator I = MBB.end();
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while (I != MBB.begin()) {
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--I;
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// Working from the bottom, when we see a non-terminator
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// instruction, we're done.
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if (!isUnpredicatedTerminator(I))
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break;
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// A terminator that isn't a branch can't easily be handled
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// by this analysis.
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if (!I->getDesc().isBranch())
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return true;
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// Handle unconditional branches.
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if (I->getOpcode() == SystemZ::JMP) {
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if (!AllowModify) {
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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// If the block has any instructions after a JMP, delete them.
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while (next(I) != MBB.end())
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next(I)->eraseFromParent();
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Cond.clear();
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FBB = 0;
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// Delete the JMP if it's equivalent to a fall-through.
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if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
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TBB = 0;
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I->eraseFromParent();
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I = MBB.end();
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continue;
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}
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// TBB is used to indicate the unconditinal destination.
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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// Handle conditional branches.
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SystemZCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
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if (BranchCode == SystemZCC::INVALID)
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return true; // Can't handle indirect branch.
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// Working from the bottom, handle the first conditional branch.
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if (Cond.empty()) {
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FBB = TBB;
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TBB = I->getOperand(0).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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continue;
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}
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// Handle subsequent conditional branches. Only handle the case where all
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// conditional branches branch to the same destination.
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assert(Cond.size() == 1);
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assert(TBB);
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// Only handle the case where all conditional branches branch to
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// the same destination.
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if (TBB != I->getOperand(0).getMBB())
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return true;
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SystemZCC::CondCodes OldBranchCode = (SystemZCC::CondCodes)Cond[0].getImm();
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// If the conditions are the same, we can leave them alone.
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if (OldBranchCode == BranchCode)
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continue;
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return true;
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}
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return false;
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}
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unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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unsigned Count = 0;
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while (I != MBB.begin()) {
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--I;
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if (I->getOpcode() != SystemZ::JMP &&
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getCondFromBranchOpc(I->getOpcode()) == SystemZCC::INVALID)
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break;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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++Count;
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}
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return Count;
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}
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unsigned
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SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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@ -363,6 +494,49 @@ SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
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}
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}
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SystemZCC::CondCodes
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SystemZInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
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switch (Opc) {
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default: return SystemZCC::INVALID;
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case SystemZ::JO: return SystemZCC::O;
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case SystemZ::JH: return SystemZCC::H;
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case SystemZ::JNLE: return SystemZCC::NLE;
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case SystemZ::JL: return SystemZCC::L;
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case SystemZ::JNHE: return SystemZCC::NHE;
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case SystemZ::JLH: return SystemZCC::LH;
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case SystemZ::JNE: return SystemZCC::NE;
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case SystemZ::JE: return SystemZCC::E;
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case SystemZ::JNLH: return SystemZCC::NLH;
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case SystemZ::JHE: return SystemZCC::HE;
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case SystemZ::JNL: return SystemZCC::NL;
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case SystemZ::JLE: return SystemZCC::LE;
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case SystemZ::JNH: return SystemZCC::NH;
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case SystemZ::JNO: return SystemZCC::NO;
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}
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}
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SystemZCC::CondCodes
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SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const {
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switch (CC) {
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default:
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assert(0 && "Invalid condition!");
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case SystemZCC::O: return SystemZCC::NO;
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case SystemZCC::H: return SystemZCC::NH;
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case SystemZCC::NLE: return SystemZCC::LE;
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case SystemZCC::L: return SystemZCC::NL;
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case SystemZCC::NHE: return SystemZCC::HE;
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case SystemZCC::LH: return SystemZCC::NLH;
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case SystemZCC::NE: return SystemZCC::E;
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case SystemZCC::E: return SystemZCC::NE;
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case SystemZCC::NLH: return SystemZCC::LH;
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case SystemZCC::HE: return SystemZCC::NHE;
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case SystemZCC::NL: return SystemZCC::L;
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case SystemZCC::LE: return SystemZCC::NLE;
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case SystemZCC::NH: return SystemZCC::H;
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case SystemZCC::NO: return SystemZCC::O;
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}
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}
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const TargetInstrDesc&
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SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
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switch (Opc) {
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@ -86,10 +86,21 @@ public:
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const;
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
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virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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SystemZCC::CondCodes getOppositeCondition(SystemZCC::CondCodes CC) const;
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SystemZCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
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const TargetInstrDesc& getBrCond(SystemZCC::CondCodes CC) const;
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const TargetInstrDesc& getLongDispOpc(unsigned Opc) const;
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};
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