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ARM: enforce SRS decoding constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183611 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1768,6 +1768,7 @@ static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
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unsigned reglist = fieldFromInstruction(Insn, 0, 16);
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if (pred == 0xF) {
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// Ambiguous with RFE and SRS
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switch (Inst.getOpcode()) {
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case ARM::LDMDA:
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Inst.setOpcode(ARM::RFEDA);
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@ -1818,11 +1819,16 @@ static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
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Inst.setOpcode(ARM::SRSIB_UPD);
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break;
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default:
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if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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}
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// For stores (which become SRS's, the only operand is the mode.
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if (fieldFromInstruction(Insn, 20, 1) == 0) {
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// Check SRS encoding constraints
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if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
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fieldFromInstruction(Insn, 20, 1) == 0))
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return MCDisassembler::Fail;
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Inst.addOperand(
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MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
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return S;
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@ -1,5 +1,3 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
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# Opcode=0 Name=PHI Format=(42)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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@ -10,4 +8,10 @@
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# B6.1.10 SRS
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# Inst{19-8} = 0xd05
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# Inst{7-5} = 0b000
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0x83 0x1c 0xc5 0xf8
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# RUN: echo "0x83 0x1c 0xc5 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
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# RUN: echo "0x00 0x00 0x20 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
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# RUN: echo "0xff 0xff 0xaf 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
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# RUN: echo "0x13 0x00 0xa0 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
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# CHECK: invalid instruction encoding
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