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Enable arm pre-allocation load / store multiple optimization pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73791 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -32,6 +32,7 @@
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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@ -992,15 +993,19 @@ bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
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return Modified;
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}
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static bool IsSafeToMove(bool isLd, unsigned Base,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator E,
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SmallPtrSet<MachineInstr*, 4> MoveOps,
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const TargetRegisterInfo *TRI) {
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static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator E,
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SmallPtrSet<MachineInstr*, 4> &MemOps,
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SmallSet<unsigned, 4> &MemRegs,
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const TargetRegisterInfo *TRI) {
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// Are there stores / loads / calls between them?
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// FIXME: This is overly conservative. We should make use of alias information
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// some day.
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SmallSet<unsigned, 4> AddedRegPressure;
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while (++I != E) {
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if (MemOps.count(&*I))
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continue;
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const TargetInstrDesc &TID = I->getDesc();
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if (TID.isCall() || TID.isTerminator() || TID.hasUnmodeledSideEffects())
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return false;
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@ -1013,16 +1018,26 @@ static bool IsSafeToMove(bool isLd, unsigned Base,
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// str r1, [r0]
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// strh r5, [r0]
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// str r4, [r0, #+4]
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if (TID.mayStore() && !MoveOps.count(&*I))
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if (TID.mayStore())
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return false;
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}
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for (unsigned j = 0, NumOps = I->getNumOperands(); j != NumOps; ++j) {
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MachineOperand &MO = I->getOperand(j);
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if (MO.isReg() && MO.isDef() && TRI->regsOverlap(MO.getReg(), Base))
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (MO.isDef() && TRI->regsOverlap(Reg, Base))
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return false;
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if (Reg != Base && !MemRegs.count(Reg))
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AddedRegPressure.insert(Reg);
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}
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}
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return true;
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// Estimate register pressure increase due to the transformation.
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if (MemRegs.size() <= 4)
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// Ok if we are moving small number of instructions.
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return true;
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return AddedRegPressure.size() <= MemRegs.size() * 2;
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}
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bool
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@ -1123,29 +1138,33 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
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LastOffset = Offset;
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LastBytes = Bytes;
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LastOpcode = Opcode;
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if (++NumMove == 4)
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if (++NumMove == 8) // FIXME: Tune
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break;
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}
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if (NumMove <= 1)
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Ops.pop_back();
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else {
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SmallPtrSet<MachineInstr*, 4> MoveOps;
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for (int i = NumMove-1; i >= 0; --i)
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MoveOps.insert(Ops[i]);
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SmallPtrSet<MachineInstr*, 4> MemOps;
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SmallSet<unsigned, 4> MemRegs;
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for (int i = NumMove-1; i >= 0; --i) {
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MemOps.insert(Ops[i]);
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MemRegs.insert(Ops[i]->getOperand(0).getReg());
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}
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// Be conservative, if the instructions are too far apart, don't
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// move them. We want to limit the increase of register pressure.
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bool DoMove = (LastLoc - FirstLoc) < NumMove*4;
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bool DoMove = (LastLoc - FirstLoc) <= NumMove*4; // FIXME: Tune this.
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if (DoMove)
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DoMove = IsSafeToMove(isLd, Base, FirstOp, LastOp, MoveOps, TRI);
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DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp,
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MemOps, MemRegs, TRI);
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if (!DoMove) {
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for (unsigned i = 0; i != NumMove; ++i)
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Ops.pop_back();
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} else {
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// This is the new location for the loads / stores.
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MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;
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while (InsertPos != MBB->end() && MoveOps.count(InsertPos))
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while (InsertPos != MBB->end() && MemOps.count(InsertPos))
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++InsertPos;
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// If we are moving a pair of loads / stores, see if it makes sense
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@ -1279,7 +1298,8 @@ ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
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}
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if (StopHere) {
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// Found a duplicate (a base+offset combination that's seen earlier). Backtrack.
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// Found a duplicate (a base+offset combination that's seen earlier).
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// Backtrack.
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--Loc;
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break;
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}
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@ -23,9 +23,6 @@
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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static cl::opt<bool>
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EnablePreLdStOpti("arm-pre-alloc-loadstore-opti", cl::Hidden,
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cl::desc("Enable pre-regalloc load store optimization pass"));
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static cl::opt<bool> DisableLdStOpti("disable-arm-loadstore-opti", cl::Hidden,
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cl::desc("Disable load store optimization pass"));
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static cl::opt<bool> DisableIfConversion("disable-arm-if-conversion",cl::Hidden,
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@ -155,8 +152,6 @@ bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
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bool ARMTargetMachine::addPreRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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if (!EnablePreLdStOpti)
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return false;
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// FIXME: temporarily disabling load / store optimization pass for Thumb mode.
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if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
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PM.add(createARMLoadStoreOptimizationPass(true));
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@ -1,6 +1,6 @@
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; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin -arm-pre-alloc-loadstore-opti | grep ldrd
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; RUN: llvm-as < %s | llc -mtriple=armv5-apple-darwin -arm-pre-alloc-loadstore-opti | not grep ldrd
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; RUN: llvm-as < %s | llc -mtriple=armv6-eabi -arm-pre-alloc-loadstore-opti | not grep ldrd
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; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin | grep ldrd
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; RUN: llvm-as < %s | llc -mtriple=armv5-apple-darwin | not grep ldrd
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; RUN: llvm-as < %s | llc -mtriple=armv6-eabi | not grep ldrd
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; rdar://r6949835
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@b = external global i64*
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@ -1,4 +1,4 @@
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; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 -arm-pre-alloc-loadstore-opti | grep stm | count 2
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; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | grep stm | count 2
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@"\01LC" = internal constant [32 x i8] c"Boolean Not: %d %d %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[32 x i8]*> [#uses=1]
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@"\01LC1" = internal constant [26 x i8] c"Bitwise Not: %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[26 x i8]*> [#uses=1]
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