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Make it SP, LR, PC for GPR Register Class instead of LR, SP, PC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94465 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -124,7 +124,7 @@ def FPSCR : ARMReg<1, "fpscr">;
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//
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//
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def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
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def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
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R7, R8, R9, R10, R11, R12,
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R7, R8, R9, R10, R11, R12,
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LR, SP, PC]> {
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SP, LR, PC]> {
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let MethodProtos = [{
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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