6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-19 04:29:21 +00:00
Code Issues Projects Releases Wiki Activity

Rename the load and store opcodes. The non-fp ones only have one

Browse Source 
variant worth worrying about; the fp ones have two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14362 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2004-06-24 07:37:12 +00:00
parent e7f9e0b539
commit af0492ea52
4 changed files with 40 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
lib/Target/Sparc/SparcAsmPrinter.cpp
View File

@ -428,12 +428,16 @@ void V8Printer::printOperand(const MachineInstr *MI, int opNum) {
static bool isLoadInstruction (const MachineInstr *MI) { static bool isLoadInstruction (const MachineInstr *MI) {
switch (MI->getOpcode ()) { switch (MI->getOpcode ()) {
case V8::LDSBmr: case V8::LDSB:
case V8::LDSHmr: case V8::LDSH:
case V8::LDUBmr: case V8::LDUB:
case V8::LDUHmr: case V8::LDUH:
case V8::LDmr: case V8::LD:
case V8::LDDmr: case V8::LDD:
case V8::LDFrr:
case V8::LDFri:
case V8::LDDFrr:
case V8::LDDFri:
return true; return true;
default: default:
return false; return false;
@ -442,10 +446,14 @@ static bool isLoadInstruction (const MachineInstr *MI) {
static bool isStoreInstruction (const MachineInstr *MI) { static bool isStoreInstruction (const MachineInstr *MI) {
switch (MI->getOpcode ()) { switch (MI->getOpcode ()) {
case V8::STBrm: case V8::STB:
case V8::STHrm: case V8::STH:
case V8::STrm: case V8::ST:
case V8::STDrm: case V8::STD:
case V8::STFrr:
case V8::STFri:
case V8::STDFrr:
case V8::STDFri:
return true; return true;
default: default:
return false; return false;

4
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -33,7 +33,7 @@ int SparcV8RegisterInfo::storeRegToStackSlot(
assert (RC == SparcV8::IntRegsRegisterClass assert (RC == SparcV8::IntRegsRegisterClass
&& "Can only store 32-bit values to stack slots"); && "Can only store 32-bit values to stack slots");
// On the order of operands here: think "[FrameIdx + 0] = SrcReg". // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
BuildMI (MBB, I, V8::STrm, 3).addFrameIndex (FrameIdx).addSImm (0).addReg (SrcReg); BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0).addReg (SrcReg);
return 1; return 1;
} }
@ -45,7 +45,7 @@ int SparcV8RegisterInfo::loadRegFromStackSlot(
{ {
assert (RC == SparcV8::IntRegsRegisterClass assert (RC == SparcV8::IntRegsRegisterClass
&& "Can only load 32-bit registers from stack slots"); && "Can only load 32-bit registers from stack slots");
BuildMI (MBB, I, V8::LDmr, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0); BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
return 1; return 1;
} }

28
lib/Target/SparcV8/SparcV8AsmPrinter.cpp
View File

@ -428,12 +428,16 @@ void V8Printer::printOperand(const MachineInstr *MI, int opNum) {
static bool isLoadInstruction (const MachineInstr *MI) { static bool isLoadInstruction (const MachineInstr *MI) {
switch (MI->getOpcode ()) { switch (MI->getOpcode ()) {
case V8::LDSBmr: case V8::LDSB:
case V8::LDSHmr: case V8::LDSH:
case V8::LDUBmr: case V8::LDUB:
case V8::LDUHmr: case V8::LDUH:
case V8::LDmr: case V8::LD:
case V8::LDDmr: case V8::LDD:
case V8::LDFrr:
case V8::LDFri:
case V8::LDDFrr:
case V8::LDDFri:
return true; return true;
default: default:
return false; return false;
@ -442,10 +446,14 @@ static bool isLoadInstruction (const MachineInstr *MI) {
static bool isStoreInstruction (const MachineInstr *MI) { static bool isStoreInstruction (const MachineInstr *MI) {
switch (MI->getOpcode ()) { switch (MI->getOpcode ()) {
case V8::STBrm: case V8::STB:
case V8::STHrm: case V8::STH:
case V8::STrm: case V8::ST:
case V8::STDrm: case V8::STD:
case V8::STFrr:
case V8::STFri:
case V8::STDFrr:
case V8::STDFri:
return true; return true;
default: default:
return false; return false;

4
lib/Target/SparcV8/SparcV8RegisterInfo.cpp
View File

@ -33,7 +33,7 @@ int SparcV8RegisterInfo::storeRegToStackSlot(
assert (RC == SparcV8::IntRegsRegisterClass assert (RC == SparcV8::IntRegsRegisterClass
&& "Can only store 32-bit values to stack slots"); && "Can only store 32-bit values to stack slots");
// On the order of operands here: think "[FrameIdx + 0] = SrcReg". // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
BuildMI (MBB, I, V8::STrm, 3).addFrameIndex (FrameIdx).addSImm (0).addReg (SrcReg); BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0).addReg (SrcReg);
return 1; return 1;
} }
@ -45,7 +45,7 @@ int SparcV8RegisterInfo::loadRegFromStackSlot(
{ {
assert (RC == SparcV8::IntRegsRegisterClass assert (RC == SparcV8::IntRegsRegisterClass
&& "Can only load 32-bit registers from stack slots"); && "Can only load 32-bit registers from stack slots");
BuildMI (MBB, I, V8::LDmr, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0); BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
return 1; return 1;
} }