6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-29 10:25:12 +00:00
Code Issues Projects Releases Wiki Activity

Fix printing of immediate operands by looking at their operand types in

Browse Source 
the TargetInstrInfo.  This fixes UnitTests 2003-05-26-Shorts and
2003-07-09-LoadShorts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15296 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
2004-07-28 00:00:48 +00:00
parent 8c02c1cbb8
commit af313fb188
3 changed files with 78 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
lib/Target/PowerPC/PPC32AsmPrinter.cpp
View File

@@ -75,6 +75,7 @@ namespace {
void printMachineInstruction(const MachineInstr *MI); void printMachineInstruction(const MachineInstr *MI);
void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false); void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
void printImmOp(const MachineOperand &MO, unsigned ArgType);
void printConstantPool(MachineConstantPool *MCP); void printConstantPool(MachineConstantPool *MCP);
bool runOnMachineFunction(MachineFunction &F); bool runOnMachineFunction(MachineFunction &F);
bool doInitialization(Module &M); bool doInitialization(Module &M);
@@ -419,11 +420,9 @@ void Printer::printOp(const MachineOperand &MO,
return; return;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_SignExtendedImmed:
O << (short)MO.getImmedValue();
return;
case MachineOperand::MO_UnextendedImmed: case MachineOperand::MO_UnextendedImmed:
O << (unsigned short)MO.getImmedValue(); std::cerr << "printOp() does not handle immediate values\n";
abort();
return; return;
case MachineOperand::MO_PCRelativeDisp: case MachineOperand::MO_PCRelativeDisp:
@@ -479,6 +478,17 @@ void Printer::printOp(const MachineOperand &MO,
} }
} }
void Printer::printImmOp(const MachineOperand &MO, unsigned ArgType) {
int Imm = MO.getImmedValue();
if (ArgType == PPC32II::Simm16 || ArgType == PPC32II::Disimm16) {
O << (short)Imm;
} else if (ArgType == PPC32II::Zimm16) {
O << (unsigned short)Imm;
} else {
O << Imm;
}
}
/// printMachineInstruction -- Print out a single PPC32 LLVM instruction /// printMachineInstruction -- Print out a single PPC32 LLVM instruction
/// MI in Darwin syntax to the current output stream. /// MI in Darwin syntax to the current output stream.
/// ///
@@ -486,11 +496,10 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
unsigned Opcode = MI->getOpcode(); unsigned Opcode = MI->getOpcode();
const TargetInstrInfo &TII = *TM.getInstrInfo(); const TargetInstrInfo &TII = *TM.getInstrInfo();
const TargetInstrDescriptor &Desc = TII.get(Opcode); const TargetInstrDescriptor &Desc = TII.get(Opcode);
unsigned int i; unsigned i;
unsigned int ArgCount = MI->getNumOperands(); unsigned ArgCount = MI->getNumOperands();
//Desc.TSFlags & PPC32II::ArgCountMask; unsigned ArgType[] = {
unsigned int ArgType[] = {
(Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask, (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask, (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask, (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask,
@@ -516,15 +525,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
O << "\n"; O << "\n";
return; return;
} else if (Opcode == PPC32::CALLpcrel) { } else if (Opcode == PPC32::CALLpcrel) {
O << TII.getName(MI->getOpcode()) << " "; O << TII.getName(Opcode) << " ";
printOp(MI->getOperand(0)); printOp(MI->getOperand(0));
O << "\n"; O << "\n";
return; return;
} else if (Opcode == PPC32::CALLindirect) { } else if (Opcode == PPC32::CALLindirect) {
O << TII.getName(MI->getOpcode()) << " "; O << TII.getName(Opcode) << " ";
printOp(MI->getOperand(0)); printImmOp(MI->getOperand(0), ArgType[0]);
O << ", "; O << ", ";
printOp(MI->getOperand(1)); printImmOp(MI->getOperand(1), ArgType[0]);
O << "\n"; O << "\n";
return; return;
} else if (Opcode == PPC32::MovePCtoLR) { } else if (Opcode == PPC32::MovePCtoLR) {
@@ -537,7 +546,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
return; return;
} }
O << TII.getName(MI->getOpcode()) << " "; O << TII.getName(Opcode) << " ";
if (Opcode == PPC32::LOADLoDirect || Opcode == PPC32::LOADLoIndirect) { if (Opcode == PPC32::LOADLoDirect || Opcode == PPC32::LOADLoIndirect) {
printOp(MI->getOperand(0)); printOp(MI->getOperand(0));
O << ", lo16("; O << ", lo16(";
@@ -562,7 +571,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
} else if (ArgCount == 3 && ArgType[1] == PPC32II::Disimm16) { } else if (ArgCount == 3 && ArgType[1] == PPC32II::Disimm16) {
printOp(MI->getOperand(0)); printOp(MI->getOperand(0));
O << ", "; O << ", ";
printOp(MI->getOperand(1)); printImmOp(MI->getOperand(1), ArgType[1]);
O << "("; O << "(";
if (MI->getOperand(2).hasAllocatedReg() && if (MI->getOperand(2).hasAllocatedReg() &&
MI->getOperand(2).getReg() == PPC32::R0) MI->getOperand(2).getReg() == PPC32::R0)
@@ -584,6 +593,8 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
assert(8 == MI->getOperand(i).getImmedValue() assert(8 == MI->getOperand(i).getImmedValue()
&& "branch off PC not to pc+8?"); && "branch off PC not to pc+8?");
//printOp(MI->getOperand(i)); //printOp(MI->getOperand(i));
} else if (MI->getOperand(i).isImmediate()) {
printImmOp(MI->getOperand(i), ArgType[i]);
} else { } else {
printOp(MI->getOperand(i)); printOp(MI->getOperand(i));
} }

39
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@@ -75,6 +75,7 @@ namespace {
void printMachineInstruction(const MachineInstr *MI); void printMachineInstruction(const MachineInstr *MI);
void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false); void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
void printImmOp(const MachineOperand &MO, unsigned ArgType);
void printConstantPool(MachineConstantPool *MCP); void printConstantPool(MachineConstantPool *MCP);
bool runOnMachineFunction(MachineFunction &F); bool runOnMachineFunction(MachineFunction &F);
bool doInitialization(Module &M); bool doInitialization(Module &M);
@@ -419,11 +420,9 @@ void Printer::printOp(const MachineOperand &MO,
return; return;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_SignExtendedImmed:
O << (short)MO.getImmedValue();
return;
case MachineOperand::MO_UnextendedImmed: case MachineOperand::MO_UnextendedImmed:
O << (unsigned short)MO.getImmedValue(); std::cerr << "printOp() does not handle immediate values\n";
abort();
return; return;
case MachineOperand::MO_PCRelativeDisp: case MachineOperand::MO_PCRelativeDisp:
@@ -479,6 +478,17 @@ void Printer::printOp(const MachineOperand &MO,
} }
} }
void Printer::printImmOp(const MachineOperand &MO, unsigned ArgType) {
int Imm = MO.getImmedValue();
if (ArgType == PPC32II::Simm16 || ArgType == PPC32II::Disimm16) {
O << (short)Imm;
} else if (ArgType == PPC32II::Zimm16) {
O << (unsigned short)Imm;
} else {
O << Imm;
}
}
/// printMachineInstruction -- Print out a single PPC32 LLVM instruction /// printMachineInstruction -- Print out a single PPC32 LLVM instruction
/// MI in Darwin syntax to the current output stream. /// MI in Darwin syntax to the current output stream.
/// ///
@@ -486,11 +496,10 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
unsigned Opcode = MI->getOpcode(); unsigned Opcode = MI->getOpcode();
const TargetInstrInfo &TII = *TM.getInstrInfo(); const TargetInstrInfo &TII = *TM.getInstrInfo();
const TargetInstrDescriptor &Desc = TII.get(Opcode); const TargetInstrDescriptor &Desc = TII.get(Opcode);
unsigned int i; unsigned i;
unsigned int ArgCount = MI->getNumOperands(); unsigned ArgCount = MI->getNumOperands();
//Desc.TSFlags & PPC32II::ArgCountMask; unsigned ArgType[] = {
unsigned int ArgType[] = {
(Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask, (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask, (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask, (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask,
@@ -516,15 +525,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
O << "\n"; O << "\n";
return; return;
} else if (Opcode == PPC32::CALLpcrel) { } else if (Opcode == PPC32::CALLpcrel) {
O << TII.getName(MI->getOpcode()) << " "; O << TII.getName(Opcode) << " ";
printOp(MI->getOperand(0)); printOp(MI->getOperand(0));
O << "\n"; O << "\n";
return; return;
} else if (Opcode == PPC32::CALLindirect) { } else if (Opcode == PPC32::CALLindirect) {
O << TII.getName(MI->getOpcode()) << " "; O << TII.getName(Opcode) << " ";
printOp(MI->getOperand(0)); printImmOp(MI->getOperand(0), ArgType[0]);
O << ", "; O << ", ";
printOp(MI->getOperand(1)); printImmOp(MI->getOperand(1), ArgType[0]);
O << "\n"; O << "\n";
return; return;
} else if (Opcode == PPC32::MovePCtoLR) { } else if (Opcode == PPC32::MovePCtoLR) {
@@ -537,7 +546,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
return; return;
} }
O << TII.getName(MI->getOpcode()) << " "; O << TII.getName(Opcode) << " ";
if (Opcode == PPC32::LOADLoDirect || Opcode == PPC32::LOADLoIndirect) { if (Opcode == PPC32::LOADLoDirect || Opcode == PPC32::LOADLoIndirect) {
printOp(MI->getOperand(0)); printOp(MI->getOperand(0));
O << ", lo16("; O << ", lo16(";
@@ -562,7 +571,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
} else if (ArgCount == 3 && ArgType[1] == PPC32II::Disimm16) { } else if (ArgCount == 3 && ArgType[1] == PPC32II::Disimm16) {
printOp(MI->getOperand(0)); printOp(MI->getOperand(0));
O << ", "; O << ", ";
printOp(MI->getOperand(1)); printImmOp(MI->getOperand(1), ArgType[1]);
O << "("; O << "(";
if (MI->getOperand(2).hasAllocatedReg() && if (MI->getOperand(2).hasAllocatedReg() &&
MI->getOperand(2).getReg() == PPC32::R0) MI->getOperand(2).getReg() == PPC32::R0)
@@ -584,6 +593,8 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
assert(8 == MI->getOperand(i).getImmedValue() assert(8 == MI->getOperand(i).getImmedValue()
&& "branch off PC not to pc+8?"); && "branch off PC not to pc+8?");
//printOp(MI->getOperand(i)); //printOp(MI->getOperand(i));
} else if (MI->getOperand(i).isImmediate()) {
printImmOp(MI->getOperand(i), ArgType[i]);
} else { } else {
printOp(MI->getOperand(i)); printOp(MI->getOperand(i));
} }

39
lib/Target/PowerPC/PowerPCAsmPrinter.cpp
View File

@@ -75,6 +75,7 @@ namespace {
void printMachineInstruction(const MachineInstr *MI); void printMachineInstruction(const MachineInstr *MI);
void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false); void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
void printImmOp(const MachineOperand &MO, unsigned ArgType);
void printConstantPool(MachineConstantPool *MCP); void printConstantPool(MachineConstantPool *MCP);
bool runOnMachineFunction(MachineFunction &F); bool runOnMachineFunction(MachineFunction &F);
bool doInitialization(Module &M); bool doInitialization(Module &M);
@@ -419,11 +420,9 @@ void Printer::printOp(const MachineOperand &MO,
return; return;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_SignExtendedImmed:
O << (short)MO.getImmedValue();
return;
case MachineOperand::MO_UnextendedImmed: case MachineOperand::MO_UnextendedImmed:
O << (unsigned short)MO.getImmedValue(); std::cerr << "printOp() does not handle immediate values\n";
abort();
return; return;
case MachineOperand::MO_PCRelativeDisp: case MachineOperand::MO_PCRelativeDisp:
@@ -479,6 +478,17 @@ void Printer::printOp(const MachineOperand &MO,
} }
} }
void Printer::printImmOp(const MachineOperand &MO, unsigned ArgType) {
int Imm = MO.getImmedValue();
if (ArgType == PPC32II::Simm16 || ArgType == PPC32II::Disimm16) {
O << (short)Imm;
} else if (ArgType == PPC32II::Zimm16) {
O << (unsigned short)Imm;
} else {
O << Imm;
}
}
/// printMachineInstruction -- Print out a single PPC32 LLVM instruction /// printMachineInstruction -- Print out a single PPC32 LLVM instruction
/// MI in Darwin syntax to the current output stream. /// MI in Darwin syntax to the current output stream.
/// ///
@@ -486,11 +496,10 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
unsigned Opcode = MI->getOpcode(); unsigned Opcode = MI->getOpcode();
const TargetInstrInfo &TII = *TM.getInstrInfo(); const TargetInstrInfo &TII = *TM.getInstrInfo();
const TargetInstrDescriptor &Desc = TII.get(Opcode); const TargetInstrDescriptor &Desc = TII.get(Opcode);
unsigned int i; unsigned i;
unsigned int ArgCount = MI->getNumOperands(); unsigned ArgCount = MI->getNumOperands();
//Desc.TSFlags & PPC32II::ArgCountMask; unsigned ArgType[] = {
unsigned int ArgType[] = {
(Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask, (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask, (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask,
(Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask, (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask,
@@ -516,15 +525,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
O << "\n"; O << "\n";
return; return;
} else if (Opcode == PPC32::CALLpcrel) { } else if (Opcode == PPC32::CALLpcrel) {
O << TII.getName(MI->getOpcode()) << " "; O << TII.getName(Opcode) << " ";
printOp(MI->getOperand(0)); printOp(MI->getOperand(0));
O << "\n"; O << "\n";
return; return;
} else if (Opcode == PPC32::CALLindirect) { } else if (Opcode == PPC32::CALLindirect) {
O << TII.getName(MI->getOpcode()) << " "; O << TII.getName(Opcode) << " ";
printOp(MI->getOperand(0)); printImmOp(MI->getOperand(0), ArgType[0]);
O << ", "; O << ", ";
printOp(MI->getOperand(1)); printImmOp(MI->getOperand(1), ArgType[0]);
O << "\n"; O << "\n";
return; return;
} else if (Opcode == PPC32::MovePCtoLR) { } else if (Opcode == PPC32::MovePCtoLR) {
@@ -537,7 +546,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
return; return;
} }
O << TII.getName(MI->getOpcode()) << " "; O << TII.getName(Opcode) << " ";
if (Opcode == PPC32::LOADLoDirect || Opcode == PPC32::LOADLoIndirect) { if (Opcode == PPC32::LOADLoDirect || Opcode == PPC32::LOADLoIndirect) {
printOp(MI->getOperand(0)); printOp(MI->getOperand(0));
O << ", lo16("; O << ", lo16(";
@@ -562,7 +571,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
} else if (ArgCount == 3 && ArgType[1] == PPC32II::Disimm16) { } else if (ArgCount == 3 && ArgType[1] == PPC32II::Disimm16) {
printOp(MI->getOperand(0)); printOp(MI->getOperand(0));
O << ", "; O << ", ";
printOp(MI->getOperand(1)); printImmOp(MI->getOperand(1), ArgType[1]);
O << "("; O << "(";
if (MI->getOperand(2).hasAllocatedReg() && if (MI->getOperand(2).hasAllocatedReg() &&
MI->getOperand(2).getReg() == PPC32::R0) MI->getOperand(2).getReg() == PPC32::R0)
@@ -584,6 +593,8 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
assert(8 == MI->getOperand(i).getImmedValue() assert(8 == MI->getOperand(i).getImmedValue()
&& "branch off PC not to pc+8?"); && "branch off PC not to pc+8?");
//printOp(MI->getOperand(i)); //printOp(MI->getOperand(i));
} else if (MI->getOperand(i).isImmediate()) {
printImmOp(MI->getOperand(i), ArgType[i]);
} else { } else {
printOp(MI->getOperand(i)); printOp(MI->getOperand(i));
} }