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[Mips Assembler] Add support for OR macro with imediate opperand
Mips assembler supports macros that allows the OR instruction to have an immediate parameter. This patch adds an instruction alias that converts this macro into a Mips ORI instruction. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -342,7 +342,9 @@ def : InstAlias<"daddu $rs, $rt, $imm",
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def : InstAlias<"dadd $rs, $rt, $imm",
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(DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
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1>;
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def : InstAlias<"or $rs, $rt, $imm",
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(ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
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1>, Requires<[HasMips64]>;
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/// Move between CPU and coprocessor registers
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let DecoderNamespace = "Mips64" in {
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@ -1015,6 +1015,9 @@ def : InstAlias<"slt $rs, $rt, $imm",
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def : InstAlias<"xor $rs, $rt, $imm",
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(XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>,
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Requires<[NotMips64]>;
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def : InstAlias<"or $rs, $rt, $imm",
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(ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>,
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Requires<[NotMips64]>;
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def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
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def : InstAlias<"mfc0 $rt, $rd",
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(MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
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@ -13,6 +13,7 @@
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# CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d]
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# CHECK: nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00]
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# CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00]
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# CHECK: ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34]
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# CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34]
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# CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00]
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# CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
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@ -40,6 +41,7 @@
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ins $19, $9, 6,7
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nor $9, $6, $7
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or $3, $3, $5
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or $4, $5, 17767
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ori $9, $6, 17767
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rotr $9, $6, 7
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rotrv $9, $6, $7
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