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[Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224989 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-12-30 15:44:17 +00:00
parent cc794daa67
commit af9e1c79a5
4 changed files with 60 additions and 14 deletions
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47
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -12,14 +12,24 @@
//===----------------------------------------------------------------------===//
let hasSideEffects = 0 in
class T_Immext<dag ins> :
EXTENDERInst<(outs), ins, "immext(#$imm)", []>,
Requires<[HasV4T]>;
class T_Immext<Operand ImmType>
: EXTENDERInst<(outs), (ins ImmType:$imm),
"immext(#$imm)", []> {
bits<32> imm;
let IClass = 0b0000;
def IMMEXT_b : T_Immext<(ins brtarget:$imm)>;
def IMMEXT_c : T_Immext<(ins calltarget:$imm)>;
def IMMEXT_g : T_Immext<(ins globaladdress:$imm)>;
def IMMEXT_i : T_Immext<(ins u26_6Imm:$imm)>;
let Inst{27-16} = imm{31-20};
let Inst{13-0} = imm{19-6};
}
def A4_ext : T_Immext<u26_6Imm>;
let isCodeGenOnly = 1 in {
let isBranch = 1 in
def A4_ext_b : T_Immext<brtarget>;
let isCall = 1 in
def A4_ext_c : T_Immext<calltarget>;
def A4_ext_g : T_Immext<globaladdress>;
}
// Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
@ -95,6 +105,29 @@ def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
//===----------------------------------------------------------------------===//
// ALU32 +
//===----------------------------------------------------------------------===//
class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
bit OpsRev>
: T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
}
let BaseOpcode = "andn_rr", CextOpcode = "andn", isCodeGenOnly = 0 in
def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
let BaseOpcode = "orn_rr", CextOpcode = "orn", isCodeGenOnly = 0 in
def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
let CextOpcode = "rcmp.eq", isCodeGenOnly = 0 in
def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
let CextOpcode = "!rcmp.eq", isCodeGenOnly = 0 in
def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
let isCodeGenOnly = 0 in {
def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
}
// Generate frame index addresses.
let hasSideEffects = 0, isReMaterializable = 1,
isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in

6
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
View File

@ -273,7 +273,7 @@ static bool IsIndirectCall(MachineInstr* MI) {
void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
MachineFunction *MF = MI->getParent()->getParent();
MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::A4_ext),
MI->getDebugLoc());
if (ResourceTracker->canReserveResources(PseudoMI)) {
@ -291,7 +291,7 @@ bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
"Should only be called for constant extended instructions");
MachineFunction *MF = MI->getParent()->getParent();
MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::A4_ext),
MI->getDebugLoc());
bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
MF->DeleteMachineInstr(PseudoMI);
@ -303,7 +303,7 @@ bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
MachineFunction *MF = MI->getParent()->getParent();
MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::A4_ext),
MI->getDebugLoc());
if (ResourceTracker->canReserveResources(PseudoMI)) {

12
test/MC/Disassembler/Hexagon/alu32_alu.txt
View File

@ -6,16 +6,20 @@
# CHECK: r17 = add(r21, r31)
0x11 0xdf 0x55 0xf6
# CHECK: r17 = add(r21, r31):sat
0x11 0xdf 0x15 0xf1
# CHECK: r17 = and(r21, r31)
0xf1 0xc3 0x15 0x76
# CHECK: r17 = and(r21, #31)
0x11 0xdf 0x35 0xf1
# CHECK: r17 = or(r21, r31)
0xf1 0xc3 0x95 0x76
# CHECK: r17 = or(r21, #31)
0x11 0xdf 0x15 0xf1
# CHECK: r17 = and(r21, r31)
0x11 0xdf 0x35 0xf1
# CHECK: r17 = or(r21, r31)
0x11 0xdf 0x75 0xf1
# CHECK: r17 = xor(r21, r31)
0x11 0xd5 0x9f 0xf1
# CHECK: r17 = and(r21, ~r31)
0x11 0xd5 0xbf 0xf1
# CHECK: r17 = or(r21, ~r31)
0x00 0xc0 0x00 0x7f
# CHECK: nop
0xb1 0xc2 0x5f 0x76

9
test/MC/Disassembler/Hexagon/alu32_pred.txt
View File

@ -50,8 +50,17 @@
# CHECK: if (p3) r17 = zxth(r21)
0x03 0xdf 0x15 0xf2
# CHECK: p3 = cmp.eq(r21, r31)
0x13 0xdf 0x15 0xf2
# CHECK: p3 = !cmp.eq(r21, r31)
0x03 0xdf 0x55 0xf2
# CHECK: p3 = cmp.gt(r21, r31)
0x13 0xdf 0x55 0xf2
# CHECK: p3 = !cmp.gt(r21, r31)
0x03 0xdf 0x75 0xf2
# CHECK: p3 = cmp.gtu(r21, r31)
0x13 0xdf 0x75 0xf2
# CHECK: p3 = !cmp.gtu(r21, r31)
0x11 0xdf 0x55 0xf3
# CHECK: r17 = cmp.eq(r21, r31)
0x11 0xdf 0x75 0xf3
# CHECK: r17 = !cmp.eq(r21, r31)