6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 20:29:48 +00:00
Code Issues Projects Releases Wiki Activity

Changes to make new TargetRegisterClass interface.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5050 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2002-12-15 19:29:34 +00:00
parent 0f24e33b73
commit afe628c1d6
1 changed files with 32 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

93
lib/Target/X86/X86RegisterClasses.cpp
View File

@ -14,97 +14,68 @@ enum {
}; };
namespace { namespace {
static const unsigned X86ByteRegisterClassRegs[] = { const unsigned ByteRegClassRegs[] = {
#define R(ENUM, NAME, FLAGS, TSFLAGS) #define R(ENUM, NAME, FLAGS, TSFLAGS)
#define R8(ENUM, NAME, FLAGS, TSFLAGS) ENUM, #define R8(ENUM, NAME, FLAGS, TSFLAGS) ENUM,
#include "X86RegisterInfo.def" #include "X86RegisterInfo.def"
}; };
struct X86ByteRegisterClass : public TargetRegisterClass { TargetRegisterClass X86ByteRegisterClassInstance(1, ByteRegClassRegs,
unsigned getNumRegs() const { ByteRegClassRegs+sizeof(ByteRegClassRegs)/sizeof(ByteRegClassRegs[0]));
return sizeof(X86ByteRegisterClassRegs)/
sizeof(X86ByteRegisterClassRegs[0]);
}
unsigned getRegister(unsigned idx) const {
assert(idx < getNumRegs() && "Index out of bounds!");
return X86ByteRegisterClassRegs[idx];
}
unsigned getDataSize() const { return 1; }
} X86ByteRegisterClassInstance;
// //
// //
// //
static const unsigned X86ShortRegisterClassRegs[] = { const unsigned ShortRegClassRegs[] = {
#define R(ENUM, NAME, FLAGS, TSFLAGS) #define R(ENUM, NAME, FLAGS, TSFLAGS)
#define R16(ENUM, NAME, FLAGS, TSFLAGS) ENUM, #define R16(ENUM, NAME, FLAGS, TSFLAGS) ENUM,
#include "X86RegisterInfo.def" #include "X86RegisterInfo.def"
}; };
struct X86ShortRegisterClass : public TargetRegisterClass { TargetRegisterClass X86ShortRegisterClassInstance(2, ShortRegClassRegs,
unsigned getNumRegs() const { ShortRegClassRegs+sizeof(ShortRegClassRegs)/sizeof(ShortRegClassRegs[0]));
return sizeof(X86ShortRegisterClassRegs)/
sizeof(X86ShortRegisterClassRegs[0]); }
unsigned getRegister(unsigned idx) const {
assert(idx < getNumRegs() && "Index out of bounds!");
return X86ShortRegisterClassRegs[idx];
}
unsigned getDataSize() const { return 2; }
} X86ShortRegisterClassInstance;
// //
// //
// //
static const unsigned X86IntRegisterClassRegs[] = { const unsigned IntRegClassRegs[] = {
#define R(ENUM, NAME, FLAGS, TSFLAGS) #define R(ENUM, NAME, FLAGS, TSFLAGS)
#define R32(ENUM, NAME, FLAGS, TSFLAGS) ENUM, #define R32(ENUM, NAME, FLAGS, TSFLAGS) ENUM,
#include "X86RegisterInfo.def" #include "X86RegisterInfo.def"
}; };
struct X86IntRegisterClass : public TargetRegisterClass { TargetRegisterClass X86IntRegisterClassInstance(4, IntRegClassRegs,
unsigned getNumRegs() const { IntRegClassRegs+sizeof(IntRegClassRegs)/sizeof(IntRegClassRegs[0]));
return sizeof(X86IntRegisterClassRegs)/
sizeof(X86IntRegisterClassRegs[0]); }
unsigned getRegister(unsigned idx) const {
assert(idx < getNumRegs() && "Index out of bounds!");
return X86IntRegisterClassRegs[idx];
}
unsigned getDataSize() const { return 4; }
} X86IntRegisterClassInstance;
const TargetRegisterClass * const X86RegClasses[] = {
static const TargetRegisterClass *X86RegClasses[] = {
&X86ByteRegisterClassInstance, &X86ByteRegisterClassInstance,
&X86ShortRegisterClassInstance, &X86ShortRegisterClassInstance,
&X86IntRegisterClassInstance &X86IntRegisterClassInstance
}; };
}
const TargetRegisterClass* X86RegisterInfo::getRegClassForType(const Type* Ty) const TargetRegisterClass* X86RegisterInfo::getRegClassForType(const Type* Ty)
const const {
{ switch (Ty->getPrimitiveID()) {
switch (Ty->getPrimitiveID()) { case Type::BoolTyID:
case Type::BoolTyID: case Type::SByteTyID:
case Type::SByteTyID: case Type::UByteTyID: return &X86ByteRegisterClassInstance;
case Type::UByteTyID: return &X86ByteRegisterClassInstance; case Type::ShortTyID:
case Type::ShortTyID: case Type::UShortTyID: return &X86ShortRegisterClassInstance;
case Type::UShortTyID: return &X86ShortRegisterClassInstance; case Type::LongTyID: // None of these are handled yet!
case Type::LongTyID: // None of these are handled yet! case Type::ULongTyID: // FIXME: Treat these like ints, this is bogus!
case Type::ULongTyID: // FIXME: Treat these like ints, this is bogus!
case Type::IntTyID:
case Type::IntTyID: case Type::UIntTyID:
case Type::UIntTyID: case Type::PointerTyID: return &X86IntRegisterClassInstance;
case Type::PointerTyID: return &X86IntRegisterClassInstance;
case Type::FloatTyID:
case Type::FloatTyID: case Type::DoubleTyID:
case Type::DoubleTyID:
default:
default: assert(0 && "Invalid type to getClass!");
assert(0 && "Invalid type to getClass!"); return 0; // not reached
return 0; // not reached
}
} }
} }