6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-21 02:29:22 +00:00
Code Issues Projects Releases Wiki Activity

Add some cases to x86 OptimizeCompare to handle DEC and INC, too.

Browse Source 
While we are setting the earlier def to true, also make it live.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164056 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jan Wen Voung 2012-09-17 22:04:23 +00:00
parent 566540332f
commit b024b7014a
2 changed files with 40 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
lib/Target/X86/X86InstrInfo.cpp
View File

@ -3127,11 +3127,19 @@ inline static bool isDefConvertible(MachineInstr *MI) {
case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
case X86::DEC64m: case X86::DEC32m: case X86::DEC16m: case X86::DEC8m:
case X86::DEC64_32r: case X86::DEC64_16r:
case X86::DEC64_32m: case X86::DEC64_16m:
case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
case X86::INC64m: case X86::INC32m: case X86::INC16m: case X86::INC8m:
case X86::INC64_32r: case X86::INC64_16r:
case X86::INC64_32m: case X86::INC64_16m:
case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
@ -3371,12 +3379,14 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
Sub->getParent()->insert(MachineBasicBlock::iterator(Sub), Movr0Inst);
}
// Make sure Sub instruction defines EFLAGS.
// Make sure Sub instruction defines EFLAGS and mark the def live.
unsigned LastOperand = Sub->getNumOperands() - 1;
assert(Sub->getNumOperands() >= 2 &&
Sub->getOperand(Sub->getNumOperands()-1).isReg() &&
Sub->getOperand(Sub->getNumOperands()-1).getReg() == X86::EFLAGS &&
Sub->getOperand(LastOperand).isReg() &&
Sub->getOperand(LastOperand).getReg() == X86::EFLAGS &&
"EFLAGS should be the last operand of SUB, ADD, OR, XOR, AND");
Sub->getOperand(Sub->getNumOperands()-1).setIsDef(true);
Sub->getOperand(LastOperand).setIsDef(true);
Sub->getOperand(LastOperand).setIsDead(false);
CmpInstr->eraseFromParent();
// Modify the condition code of instructions in OpsToUpdate.

27
test/CodeGen/X86/jump_sign.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mcpu=pentiumpro | FileCheck %s
; RUN: llc < %s -march=x86 -mcpu=pentiumpro -verify-machineinstrs | FileCheck %s
define i32 @f(i32 %X) {
entry:
@ -253,3 +253,28 @@ return:
%retval.0 = phi i8* [ %add.ptr, %if.end ], [ null, %entry ]
ret i8* %retval.0
}
; Test optimizations of dec/inc.
define i32 @dec(i32 %a) nounwind {
entry:
; CHECK: dec:
; CHECK: decl
; CHECK-NOT: test
; CHECK: cmovsl
%sub = sub nsw i32 %a, 1
%cmp = icmp sgt i32 %sub, 0
%cond = select i1 %cmp, i32 %sub, i32 0
ret i32 %cond
}
define i32 @inc(i32 %a) nounwind {
entry:
; CHECK: inc:
; CHECK: incl
; CHECK-NOT: test
; CHECK: cmovsl
%add = add nsw i32 %a, 1
%cmp = icmp sgt i32 %add, 0
%cond = select i1 %cmp, i32 %add, i32 0
ret i32 %cond
}