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Fix PR4986. "r1024 = insert_subreg r1024, undef, 2" cannot be turned in an implicit_def. Instead, it's an identity copy so it should be eliminated. Also make sure to update livevariable kill information.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82436 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-09-21 04:32:32 +00:00
parent cc1c702f62
commit b0f5973bee
2 changed files with 57 additions and 10 deletions
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33
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -109,18 +109,15 @@ void LiveIntervals::releaseMemory() {
}
static bool CanTurnIntoImplicitDef(MachineInstr *MI, unsigned Reg,
const TargetInstrInfo *tii_) {
unsigned OpIdx, const TargetInstrInfo *tii_){
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
Reg == SrcReg)
return true;
if ((MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
MI->getOperand(2).getReg() == Reg)
if (OpIdx == 2 && MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG)
return true;
if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG &&
MI->getOperand(1).getReg() == Reg)
if (OpIdx == 1 && MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)
return true;
return false;
}
@ -148,6 +145,20 @@ void LiveIntervals::processImplicitDefs() {
continue;
}
if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
MachineOperand &MO = MI->getOperand(2);
if (ImpDefRegs.count(MO.getReg())) {
// %reg1032<def> = INSERT_SUBREG %reg1032, undef, 2
// This is an identity copy, eliminate it now.
if (MO.isKill()) {
LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg());
vi.removeKill(MI);
}
MI->eraseFromParent();
continue;
}
}
bool ChangedToImpDef = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
@ -159,13 +170,16 @@ void LiveIntervals::processImplicitDefs() {
if (!ImpDefRegs.count(Reg))
continue;
// Use is a copy, just turn it into an implicit_def.
if (CanTurnIntoImplicitDef(MI, Reg, tii_)) {
if (CanTurnIntoImplicitDef(MI, Reg, i, tii_)) {
bool isKill = MO.isKill();
MI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
MI->RemoveOperand(j);
if (isKill)
if (isKill) {
ImpDefRegs.erase(Reg);
LiveVariables::VarInfo& vi = lv_->getVarInfo(Reg);
vi.removeKill(MI);
}
ChangedToImpDef = true;
break;
}
@ -738,8 +752,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
MachineInstr *Kill = vi.Kills[i];
MachineInstrIndex killIdx =
getNextSlot(getUseIndex(getInstructionIndex(Kill)));
LiveRange LR(getMBBStartIdx(Kill->getParent()),
killIdx, ValNo);
LiveRange LR(getMBBStartIdx(Kill->getParent()), killIdx, ValNo);
interval.addRange(LR);
ValNo->addKill(killIdx);
DEBUG(errs() << " +" << LR);

34
test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll Normal file
View File

@ -0,0 +1,34 @@
; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a9
; PR4986
define arm_aapcs_vfpcc void @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
entry:
br i1 undef, label %return, label %bb.preheader
bb.preheader: ; preds = %entry
br label %bb
bb: ; preds = %bb, %bb.preheader
%0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
%1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1]
%2 = insertelement <4 x float> %1, float undef, i32 2 ; <<4 x float>> [#uses=1]
%3 = insertelement <4 x float> %2, float undef, i32 3 ; <<4 x float>> [#uses=1]
%4 = fmul <4 x float> undef, %3 ; <<4 x float>> [#uses=1]
%5 = extractelement <4 x float> %4, i32 3 ; <float> [#uses=1]
store float %5, float* undef, align 4
br i1 undef, label %return, label %bb
return: ; preds = %bb, %entry
ret void
}
define arm_aapcs_vfpcc <4 x float> @bar(i8* nocapture %pBuffer, i32 %numItems) nounwind {
%1 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
%2 = insertelement <4 x float> %1, float undef, i32 1 ; <<4 x float>> [#uses=1]
%3 = insertelement <4 x float> %2, float undef, i32 2 ; <<4 x float>> [#uses=1]
%4 = insertelement <4 x float> %3, float undef, i32 3 ; <<4 x float>> [#uses=1]
%5 = shufflevector <4 x float> %4, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
%6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1]
ret <4 x float> %6
}