mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-27 15:29:51 +00:00
Reorganize code a bit to reduce indentation. No visible functionality
change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77171 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman
parent
d42b58b61c
commit
b101b0bdbd
@ -1518,321 +1518,321 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
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case ISD::SETTRUE2: return DAG.getConstant(1, VT);
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}
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if (isa<ConstantSDNode>(N0.getNode())) {
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// Ensure that the constant occurs on the RHS, and fold constant
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// comparisons.
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return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
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}
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if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
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const APInt &C1 = N1C->getAPIntValue();
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if (isa<ConstantSDNode>(N0.getNode())) {
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return DAG.FoldSetCC(VT, N0, N1, Cond, dl);
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} else {
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// If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
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// equality comparison, then we're just comparing whether X itself is
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// zero.
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if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
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N0.getOperand(0).getOpcode() == ISD::CTLZ &&
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N0.getOperand(1).getOpcode() == ISD::Constant) {
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unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
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if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
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ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
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if ((C1 == 0) == (Cond == ISD::SETEQ)) {
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// (srl (ctlz x), 5) == 0 -> X != 0
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// (srl (ctlz x), 5) != 1 -> X != 0
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Cond = ISD::SETNE;
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} else {
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// (srl (ctlz x), 5) != 0 -> X == 0
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// (srl (ctlz x), 5) == 1 -> X == 0
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Cond = ISD::SETEQ;
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}
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SDValue Zero = DAG.getConstant(0, N0.getValueType());
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return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
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Zero, Cond);
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}
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}
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// If the LHS is '(and load, const)', the RHS is 0,
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// the test is for equality or unsigned, and all 1 bits of the const are
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// in the same partial word, see if we can shorten the load.
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if (DCI.isBeforeLegalize() &&
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N0.getOpcode() == ISD::AND && C1 == 0 &&
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N0.getNode()->hasOneUse() &&
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isa<LoadSDNode>(N0.getOperand(0)) &&
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N0.getOperand(0).getNode()->hasOneUse() &&
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isa<ConstantSDNode>(N0.getOperand(1))) {
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LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
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uint64_t bestMask = 0;
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unsigned bestWidth = 0, bestOffset = 0;
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if (!Lod->isVolatile() && Lod->isUnindexed() &&
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// FIXME: This uses getZExtValue() below so it only works on i64 and
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// below.
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N0.getValueType().getSizeInBits() <= 64) {
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unsigned origWidth = N0.getValueType().getSizeInBits();
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// We can narrow (e.g.) 16-bit extending loads on 32-bit target to
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// 8 bits, but have to be careful...
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if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
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origWidth = Lod->getMemoryVT().getSizeInBits();
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uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
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for (unsigned width = origWidth / 2; width>=8; width /= 2) {
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uint64_t newMask = (1ULL << width) - 1;
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for (unsigned offset=0; offset<origWidth/width; offset++) {
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if ((newMask & Mask) == Mask) {
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if (!TD->isLittleEndian())
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bestOffset = (origWidth/width - offset - 1) * (width/8);
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else
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bestOffset = (uint64_t)offset * (width/8);
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bestMask = Mask >> (offset * (width/8) * 8);
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bestWidth = width;
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break;
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}
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newMask = newMask << width;
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// If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
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// equality comparison, then we're just comparing whether X itself is
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// zero.
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if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
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N0.getOperand(0).getOpcode() == ISD::CTLZ &&
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N0.getOperand(1).getOpcode() == ISD::Constant) {
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unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
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if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
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ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
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if ((C1 == 0) == (Cond == ISD::SETEQ)) {
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// (srl (ctlz x), 5) == 0 -> X != 0
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// (srl (ctlz x), 5) != 1 -> X != 0
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Cond = ISD::SETNE;
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} else {
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// (srl (ctlz x), 5) != 0 -> X == 0
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// (srl (ctlz x), 5) == 1 -> X == 0
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Cond = ISD::SETEQ;
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}
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SDValue Zero = DAG.getConstant(0, N0.getValueType());
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return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
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Zero, Cond);
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}
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}
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// If the LHS is '(and load, const)', the RHS is 0,
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// the test is for equality or unsigned, and all 1 bits of the const are
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// in the same partial word, see if we can shorten the load.
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if (DCI.isBeforeLegalize() &&
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N0.getOpcode() == ISD::AND && C1 == 0 &&
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N0.getNode()->hasOneUse() &&
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isa<LoadSDNode>(N0.getOperand(0)) &&
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N0.getOperand(0).getNode()->hasOneUse() &&
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isa<ConstantSDNode>(N0.getOperand(1))) {
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LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
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uint64_t bestMask = 0;
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unsigned bestWidth = 0, bestOffset = 0;
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if (!Lod->isVolatile() && Lod->isUnindexed() &&
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// FIXME: This uses getZExtValue() below so it only works on i64 and
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// below.
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N0.getValueType().getSizeInBits() <= 64) {
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unsigned origWidth = N0.getValueType().getSizeInBits();
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// We can narrow (e.g.) 16-bit extending loads on 32-bit target to
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// 8 bits, but have to be careful...
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if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
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origWidth = Lod->getMemoryVT().getSizeInBits();
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uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
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for (unsigned width = origWidth / 2; width>=8; width /= 2) {
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uint64_t newMask = (1ULL << width) - 1;
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for (unsigned offset=0; offset<origWidth/width; offset++) {
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if ((newMask & Mask) == Mask) {
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if (!TD->isLittleEndian())
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bestOffset = (origWidth/width - offset - 1) * (width/8);
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else
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bestOffset = (uint64_t)offset * (width/8);
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bestMask = Mask >> (offset * (width/8) * 8);
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bestWidth = width;
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break;
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}
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}
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}
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if (bestWidth) {
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MVT newVT = MVT::getIntegerVT(bestWidth);
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if (newVT.isRound()) {
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MVT PtrType = Lod->getOperand(1).getValueType();
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SDValue Ptr = Lod->getBasePtr();
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if (bestOffset != 0)
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Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
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DAG.getConstant(bestOffset, PtrType));
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unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
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SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
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Lod->getSrcValue(),
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Lod->getSrcValueOffset() + bestOffset,
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false, NewAlign);
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return DAG.getSetCC(dl, VT,
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DAG.getNode(ISD::AND, dl, newVT, NewLoad,
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DAG.getConstant(bestMask, newVT)),
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DAG.getConstant(0LL, newVT), Cond);
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newMask = newMask << width;
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}
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}
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}
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// If the LHS is a ZERO_EXTEND, perform the comparison on the input.
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if (N0.getOpcode() == ISD::ZERO_EXTEND) {
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unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
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// If the comparison constant has bits in the upper part, the
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// zero-extended value could never match.
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if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
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C1.getBitWidth() - InSize))) {
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switch (Cond) {
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case ISD::SETUGT:
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case ISD::SETUGE:
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case ISD::SETEQ: return DAG.getConstant(0, VT);
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case ISD::SETULT:
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case ISD::SETULE:
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case ISD::SETNE: return DAG.getConstant(1, VT);
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case ISD::SETGT:
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case ISD::SETGE:
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// True if the sign bit of C1 is set.
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return DAG.getConstant(C1.isNegative(), VT);
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case ISD::SETLT:
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case ISD::SETLE:
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// True if the sign bit of C1 isn't set.
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return DAG.getConstant(C1.isNonNegative(), VT);
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default:
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break;
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}
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if (bestWidth) {
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MVT newVT = MVT::getIntegerVT(bestWidth);
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if (newVT.isRound()) {
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MVT PtrType = Lod->getOperand(1).getValueType();
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SDValue Ptr = Lod->getBasePtr();
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if (bestOffset != 0)
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Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
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DAG.getConstant(bestOffset, PtrType));
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unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
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SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
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Lod->getSrcValue(),
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Lod->getSrcValueOffset() + bestOffset,
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false, NewAlign);
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return DAG.getSetCC(dl, VT,
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DAG.getNode(ISD::AND, dl, newVT, NewLoad,
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DAG.getConstant(bestMask, newVT)),
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DAG.getConstant(0LL, newVT), Cond);
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}
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}
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}
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// Otherwise, we can perform the comparison with the low bits.
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// If the LHS is a ZERO_EXTEND, perform the comparison on the input.
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if (N0.getOpcode() == ISD::ZERO_EXTEND) {
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unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
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// If the comparison constant has bits in the upper part, the
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// zero-extended value could never match.
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if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
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C1.getBitWidth() - InSize))) {
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switch (Cond) {
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case ISD::SETEQ:
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case ISD::SETNE:
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case ISD::SETUGT:
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case ISD::SETUGE:
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case ISD::SETEQ: return DAG.getConstant(0, VT);
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case ISD::SETULT:
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case ISD::SETULE: {
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MVT newVT = N0.getOperand(0).getValueType();
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if (DCI.isBeforeLegalizeOps() ||
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(isOperationLegal(ISD::SETCC, newVT) &&
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getCondCodeAction(Cond, newVT)==Legal))
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return DAG.getSetCC(dl, VT, N0.getOperand(0),
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DAG.getConstant(APInt(C1).trunc(InSize), newVT),
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Cond);
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case ISD::SETULE:
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case ISD::SETNE: return DAG.getConstant(1, VT);
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case ISD::SETGT:
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case ISD::SETGE:
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// True if the sign bit of C1 is set.
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return DAG.getConstant(C1.isNegative(), VT);
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case ISD::SETLT:
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case ISD::SETLE:
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// True if the sign bit of C1 isn't set.
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return DAG.getConstant(C1.isNonNegative(), VT);
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default:
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break;
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}
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default:
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break; // todo, be more careful with signed comparisons
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}
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} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
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(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
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MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
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unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
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MVT ExtDstTy = N0.getValueType();
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unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
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}
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// If the extended part has any inconsistent bits, it cannot ever
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// compare equal. In other words, they have to be all ones or all
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// zeros.
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APInt ExtBits =
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APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
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if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
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return DAG.getConstant(Cond == ISD::SETNE, VT);
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// Otherwise, we can perform the comparison with the low bits.
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switch (Cond) {
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case ISD::SETEQ:
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case ISD::SETNE:
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case ISD::SETUGT:
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case ISD::SETUGE:
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case ISD::SETULT:
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case ISD::SETULE: {
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MVT newVT = N0.getOperand(0).getValueType();
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if (DCI.isBeforeLegalizeOps() ||
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(isOperationLegal(ISD::SETCC, newVT) &&
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getCondCodeAction(Cond, newVT)==Legal))
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return DAG.getSetCC(dl, VT, N0.getOperand(0),
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DAG.getConstant(APInt(C1).trunc(InSize), newVT),
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Cond);
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break;
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}
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default:
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break; // todo, be more careful with signed comparisons
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}
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} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
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(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
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MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
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unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
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MVT ExtDstTy = N0.getValueType();
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unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
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// If the extended part has any inconsistent bits, it cannot ever
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// compare equal. In other words, they have to be all ones or all
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// zeros.
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APInt ExtBits =
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APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
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if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
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return DAG.getConstant(Cond == ISD::SETNE, VT);
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SDValue ZextOp;
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MVT Op0Ty = N0.getOperand(0).getValueType();
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if (Op0Ty == ExtSrcTy) {
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ZextOp = N0.getOperand(0);
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} else {
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APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
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ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
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DAG.getConstant(Imm, Op0Ty));
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}
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if (!DCI.isCalledByLegalizer())
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DCI.AddToWorklist(ZextOp.getNode());
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// Otherwise, make this a use of a zext.
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return DAG.getSetCC(dl, VT, ZextOp,
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DAG.getConstant(C1 & APInt::getLowBitsSet(
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ExtDstTyBits,
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ExtSrcTyBits),
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ExtDstTy),
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Cond);
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} else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
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(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
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// SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
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if (N0.getOpcode() == ISD::SETCC) {
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bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1);
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if (TrueWhenTrue)
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return N0;
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SDValue ZextOp;
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MVT Op0Ty = N0.getOperand(0).getValueType();
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if (Op0Ty == ExtSrcTy) {
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ZextOp = N0.getOperand(0);
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} else {
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APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
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ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
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DAG.getConstant(Imm, Op0Ty));
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}
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if (!DCI.isCalledByLegalizer())
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DCI.AddToWorklist(ZextOp.getNode());
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// Otherwise, make this a use of a zext.
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return DAG.getSetCC(dl, VT, ZextOp,
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DAG.getConstant(C1 & APInt::getLowBitsSet(
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ExtDstTyBits,
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ExtSrcTyBits),
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ExtDstTy),
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Cond);
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} else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
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(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
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// SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
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if (N0.getOpcode() == ISD::SETCC) {
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bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1);
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if (TrueWhenTrue)
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return N0;
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// Invert the condition.
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ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
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CC = ISD::getSetCCInverse(CC,
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N0.getOperand(0).getValueType().isInteger());
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return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
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}
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if ((N0.getOpcode() == ISD::XOR ||
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(N0.getOpcode() == ISD::AND &&
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N0.getOperand(0).getOpcode() == ISD::XOR &&
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N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
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isa<ConstantSDNode>(N0.getOperand(1)) &&
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cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
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// If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
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// can only do this if the top bits are known zero.
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unsigned BitWidth = N0.getValueSizeInBits();
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if (DAG.MaskedValueIsZero(N0,
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APInt::getHighBitsSet(BitWidth,
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BitWidth-1))) {
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// Okay, get the un-inverted input value.
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SDValue Val;
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if (N0.getOpcode() == ISD::XOR)
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Val = N0.getOperand(0);
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else {
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assert(N0.getOpcode() == ISD::AND &&
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N0.getOperand(0).getOpcode() == ISD::XOR);
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// ((X^1)&1)^1 -> X & 1
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Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
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||||
N0.getOperand(0).getOperand(0),
|
||||
N0.getOperand(1));
|
||||
}
|
||||
return DAG.getSetCC(dl, VT, Val, N1,
|
||||
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
|
||||
}
|
||||
}
|
||||
// Invert the condition.
|
||||
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
|
||||
CC = ISD::getSetCCInverse(CC,
|
||||
N0.getOperand(0).getValueType().isInteger());
|
||||
return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
|
||||
}
|
||||
|
||||
APInt MinVal, MaxVal;
|
||||
unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
|
||||
if (ISD::isSignedIntSetCC(Cond)) {
|
||||
MinVal = APInt::getSignedMinValue(OperandBitSize);
|
||||
MaxVal = APInt::getSignedMaxValue(OperandBitSize);
|
||||
} else {
|
||||
MinVal = APInt::getMinValue(OperandBitSize);
|
||||
MaxVal = APInt::getMaxValue(OperandBitSize);
|
||||
if ((N0.getOpcode() == ISD::XOR ||
|
||||
(N0.getOpcode() == ISD::AND &&
|
||||
N0.getOperand(0).getOpcode() == ISD::XOR &&
|
||||
N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
|
||||
isa<ConstantSDNode>(N0.getOperand(1)) &&
|
||||
cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
|
||||
// If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
|
||||
// can only do this if the top bits are known zero.
|
||||
unsigned BitWidth = N0.getValueSizeInBits();
|
||||
if (DAG.MaskedValueIsZero(N0,
|
||||
APInt::getHighBitsSet(BitWidth,
|
||||
BitWidth-1))) {
|
||||
// Okay, get the un-inverted input value.
|
||||
SDValue Val;
|
||||
if (N0.getOpcode() == ISD::XOR)
|
||||
Val = N0.getOperand(0);
|
||||
else {
|
||||
assert(N0.getOpcode() == ISD::AND &&
|
||||
N0.getOperand(0).getOpcode() == ISD::XOR);
|
||||
// ((X^1)&1)^1 -> X & 1
|
||||
Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
|
||||
N0.getOperand(0).getOperand(0),
|
||||
N0.getOperand(1));
|
||||
}
|
||||
return DAG.getSetCC(dl, VT, Val, N1,
|
||||
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
APInt MinVal, MaxVal;
|
||||
unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
|
||||
if (ISD::isSignedIntSetCC(Cond)) {
|
||||
MinVal = APInt::getSignedMinValue(OperandBitSize);
|
||||
MaxVal = APInt::getSignedMaxValue(OperandBitSize);
|
||||
} else {
|
||||
MinVal = APInt::getMinValue(OperandBitSize);
|
||||
MaxVal = APInt::getMaxValue(OperandBitSize);
|
||||
}
|
||||
|
||||
// Canonicalize GE/LE comparisons to use GT/LT comparisons.
|
||||
if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
|
||||
if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
|
||||
// X >= C0 --> X > (C0-1)
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(C1-1, N1.getValueType()),
|
||||
(Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
|
||||
}
|
||||
// Canonicalize GE/LE comparisons to use GT/LT comparisons.
|
||||
if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
|
||||
if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
|
||||
// X >= C0 --> X > (C0-1)
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(C1-1, N1.getValueType()),
|
||||
(Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
|
||||
}
|
||||
|
||||
if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
|
||||
if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
|
||||
// X <= C0 --> X < (C0+1)
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(C1+1, N1.getValueType()),
|
||||
(Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
|
||||
}
|
||||
if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
|
||||
if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
|
||||
// X <= C0 --> X < (C0+1)
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(C1+1, N1.getValueType()),
|
||||
(Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
|
||||
}
|
||||
|
||||
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
|
||||
return DAG.getConstant(0, VT); // X < MIN --> false
|
||||
if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
|
||||
return DAG.getConstant(1, VT); // X >= MIN --> true
|
||||
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
|
||||
return DAG.getConstant(0, VT); // X > MAX --> false
|
||||
if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
|
||||
return DAG.getConstant(1, VT); // X <= MAX --> true
|
||||
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
|
||||
return DAG.getConstant(0, VT); // X < MIN --> false
|
||||
if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
|
||||
return DAG.getConstant(1, VT); // X >= MIN --> true
|
||||
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
|
||||
return DAG.getConstant(0, VT); // X > MAX --> false
|
||||
if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
|
||||
return DAG.getConstant(1, VT); // X <= MAX --> true
|
||||
|
||||
// Canonicalize setgt X, Min --> setne X, Min
|
||||
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
|
||||
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
|
||||
// Canonicalize setlt X, Max --> setne X, Max
|
||||
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
|
||||
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
|
||||
// Canonicalize setgt X, Min --> setne X, Min
|
||||
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
|
||||
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
|
||||
// Canonicalize setlt X, Max --> setne X, Max
|
||||
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
|
||||
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
|
||||
|
||||
// If we have setult X, 1, turn it into seteq X, 0
|
||||
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(MinVal, N0.getValueType()),
|
||||
ISD::SETEQ);
|
||||
// If we have setugt X, Max-1, turn it into seteq X, Max
|
||||
else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(MaxVal, N0.getValueType()),
|
||||
ISD::SETEQ);
|
||||
// If we have setult X, 1, turn it into seteq X, 0
|
||||
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(MinVal, N0.getValueType()),
|
||||
ISD::SETEQ);
|
||||
// If we have setugt X, Max-1, turn it into seteq X, Max
|
||||
else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(MaxVal, N0.getValueType()),
|
||||
ISD::SETEQ);
|
||||
|
||||
// If we have "setcc X, C0", check to see if we can shrink the immediate
|
||||
// by changing cc.
|
||||
// If we have "setcc X, C0", check to see if we can shrink the immediate
|
||||
// by changing cc.
|
||||
|
||||
// SETUGT X, SINTMAX -> SETLT X, 0
|
||||
if (Cond == ISD::SETUGT &&
|
||||
C1 == APInt::getSignedMaxValue(OperandBitSize))
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(0, N1.getValueType()),
|
||||
ISD::SETLT);
|
||||
// SETUGT X, SINTMAX -> SETLT X, 0
|
||||
if (Cond == ISD::SETUGT &&
|
||||
C1 == APInt::getSignedMaxValue(OperandBitSize))
|
||||
return DAG.getSetCC(dl, VT, N0,
|
||||
DAG.getConstant(0, N1.getValueType()),
|
||||
ISD::SETLT);
|
||||
|
||||
// SETULT X, SINTMIN -> SETGT X, -1
|
||||
if (Cond == ISD::SETULT &&
|
||||
C1 == APInt::getSignedMinValue(OperandBitSize)) {
|
||||
SDValue ConstMinusOne =
|
||||
DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
|
||||
N1.getValueType());
|
||||
return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
|
||||
}
|
||||
// SETULT X, SINTMIN -> SETGT X, -1
|
||||
if (Cond == ISD::SETULT &&
|
||||
C1 == APInt::getSignedMinValue(OperandBitSize)) {
|
||||
SDValue ConstMinusOne =
|
||||
DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
|
||||
N1.getValueType());
|
||||
return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
|
||||
}
|
||||
|
||||
// Fold bit comparisons when we can.
|
||||
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
|
||||
VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
|
||||
if (ConstantSDNode *AndRHS =
|
||||
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
|
||||
MVT ShiftTy = DCI.isBeforeLegalize() ?
|
||||
getPointerTy() : getShiftAmountTy();
|
||||
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
|
||||
// Perform the xform if the AND RHS is a single bit.
|
||||
if (isPowerOf2_64(AndRHS->getZExtValue())) {
|
||||
return DAG.getNode(ISD::SRL, dl, VT, N0,
|
||||
DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
|
||||
ShiftTy));
|
||||
}
|
||||
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) {
|
||||
// (X & 8) == 8 --> (X & 8) >> 3
|
||||
// Perform the xform if C1 is a single bit.
|
||||
if (C1.isPowerOf2()) {
|
||||
return DAG.getNode(ISD::SRL, dl, VT, N0,
|
||||
DAG.getConstant(C1.logBase2(), ShiftTy));
|
||||
}
|
||||
// Fold bit comparisons when we can.
|
||||
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
|
||||
VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
|
||||
if (ConstantSDNode *AndRHS =
|
||||
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
|
||||
MVT ShiftTy = DCI.isBeforeLegalize() ?
|
||||
getPointerTy() : getShiftAmountTy();
|
||||
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
|
||||
// Perform the xform if the AND RHS is a single bit.
|
||||
if (isPowerOf2_64(AndRHS->getZExtValue())) {
|
||||
return DAG.getNode(ISD::SRL, dl, VT, N0,
|
||||
DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
|
||||
ShiftTy));
|
||||
}
|
||||
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) {
|
||||
// (X & 8) == 8 --> (X & 8) >> 3
|
||||
// Perform the xform if C1 is a single bit.
|
||||
if (C1.isPowerOf2()) {
|
||||
return DAG.getNode(ISD::SRL, dl, VT, N0,
|
||||
DAG.getConstant(C1.logBase2(), ShiftTy));
|
||||
}
|
||||
}
|
||||
}
|
||||
} else if (isa<ConstantSDNode>(N0.getNode())) {
|
||||
// Ensure that the constant occurs on the RHS.
|
||||
return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
|
||||
}
|
||||
}
|
||||
|
||||
if (isa<ConstantFPSDNode>(N0.getNode())) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user