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Made a fix so that you can print out MachineInstrs that belong to a MachineBasicBlock that is not yet attached to a MachineFunction. This change includes changing the third operand (TargetMachine) to a pointer for the MachineInstr::print function.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14389 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tanya Lattner
2004-06-25 00:13:11 +00:00
parent 32b588039e
commit b140762a45
11 changed files with 46 additions and 27 deletions
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6
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@@ -179,7 +179,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
for (MachineBasicBlock::iterator mii = mbbi->begin(),
mie = mbbi->end(); mii != mie; ++mii) {
std::cerr << getInstructionIndex(mii) << '\t';
mii->print(std::cerr, *tm_);
mii->print(std::cerr, tm_);
}
});
@@ -427,7 +427,7 @@ void LiveIntervals::computeIntervals()
const TargetInstrDescriptor& tid =
tm_->getInstrInfo()->get(mi->getOpcode());
DEBUG(std::cerr << getInstructionIndex(mi) << "\t";
mi->print(std::cerr, *tm_));
mi->print(std::cerr, tm_));
// handle implicit defs
for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
@@ -467,7 +467,7 @@ void LiveIntervals::joinIntervals()
mi != mie; ++mi) {
const TargetInstrDescriptor& tid = tii.get(mi->getOpcode());
DEBUG(std::cerr << getInstructionIndex(mi) << '\t';
mi->print(std::cerr, *tm_););
mi->print(std::cerr, tm_););
// we only join virtual registers with allocatable
// physical registers since we do not have liveness information

2
lib/CodeGen/MachineBasicBlock.cpp
View File

@@ -105,6 +105,6 @@ void MachineBasicBlock::print(std::ostream &OS) const
<< ", LLVM BB @" << (const void*) LBB << "):\n";
for (const_iterator I = begin(); I != end(); ++I) {
OS << "\t";
I->print(OS, getParent()->getTarget());
I->print(OS, &getParent()->getTarget());
}
}

23
lib/CodeGen/MachineInstr.cpp
View File

@@ -235,8 +235,14 @@ static inline void OutputReg(std::ostream &os, unsigned RegNo,
}
static void print(const MachineOperand &MO, std::ostream &OS,
const TargetMachine &TM) {
const MRegisterInfo *MRI = TM.getRegisterInfo();
const TargetMachine *TM) {
const MRegisterInfo *MRI = 0;
if(TM)
MRI = TM->getRegisterInfo();
bool CloseParen = true;
if (MO.isHiBits32())
OS << "%lm(";
@@ -313,7 +319,7 @@ static void print(const MachineOperand &MO, std::ostream &OS,
OS << ")";
}
void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
unsigned StartOp = 0;
// Specialize printing if op#0 is definition
@@ -322,7 +328,11 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
OS << " = ";
++StartOp; // Don't print this operand again!
}
OS << TM.getInstrInfo()->getName(getOpcode());
//Must check if Target machine is not null because machine BB could not
//be attached to a Machine function yet
if(TM)
OS << TM->getInstrInfo()->getName(getOpcode());
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
const MachineOperand& mop = getOperand(i);
@@ -361,7 +371,10 @@ std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
// info for the instruction.
if (const MachineBasicBlock *MBB = MI.getParent()) {
const MachineFunction *MF = MBB->getParent();
MI.print(os, MF->getTarget());
if(MF)
MI.print(os, &MF->getTarget());
else
MI.print(os, 0);
return os;
}

2
lib/CodeGen/RegAllocSimple.cpp
View File

@@ -177,7 +177,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
unsigned virtualReg = (unsigned) op.getReg();
DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: ";
MI->print(std::cerr, *TM));
MI->print(std::cerr, TM));
// make sure the same virtual register maps to the same physical
// register in any given instruction

6
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@@ -98,7 +98,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
++numTwoAddressInstrs;
DEBUG(std::cerr << '\t'; mi->print(std::cerr, TM));
DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
assert(mi->getOperand(1).isRegister() &&
mi->getOperand(1).getReg() &&
@@ -140,7 +140,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
MachineBasicBlock::iterator prevMi = prior(mi);
DEBUG(std::cerr << "\t\tprepend:\t";
prevMi->print(std::cerr, TM));
prevMi->print(std::cerr, &TM));
if (LV) {
// update live variables for regA
@@ -170,7 +170,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
mi->RemoveOperand(1);
DEBUG(std::cerr << "\t\trewrite to:\t";
mi->print(std::cerr, TM));
mi->print(std::cerr, &TM));
}
}

12
lib/CodeGen/VirtRegMap.cpp
View File

@@ -149,7 +149,7 @@ namespace {
mf.getSSARegMap()->getRegClass(virtReg));
loaded[virtReg] = true;
DEBUG(std::cerr << '\t';
prior(mii)->print(std::cerr, tm));
prior(mii)->print(std::cerr, &tm));
++numLoads;
}
if (mop.isDef() &&
@@ -165,7 +165,7 @@ namespace {
mii->SetMachineOperandReg(i, physReg);
}
}
DEBUG(std::cerr << '\t'; mii->print(std::cerr, tm));
DEBUG(std::cerr << '\t'; mii->print(std::cerr, &tm));
loaded.clear();
}
}
@@ -231,9 +231,9 @@ namespace {
mri_->getRegClass(physReg));
++numStores;
DEBUG(std::cerr << "added: ";
prior(nextLastRef)->print(std::cerr, *tm_);
prior(nextLastRef)->print(std::cerr, tm_);
std::cerr << "after: ";
lastDef->print(std::cerr, *tm_));
lastDef->print(std::cerr, tm_));
lastDef_[virtReg] = 0;
}
p2vMap_[physReg] = 0;
@@ -263,7 +263,7 @@ namespace {
mri_->getRegClass(physReg));
++numLoads;
DEBUG(std::cerr << "added: ";
prior(mii)->print(std::cerr, *tm_));
prior(mii)->print(std::cerr, tm_));
lastDef_[virtReg] = mii;
}
}
@@ -339,7 +339,7 @@ namespace {
}
}
DEBUG(std::cerr << '\t'; mii->print(std::cerr, *tm_));
DEBUG(std::cerr << '\t'; mii->print(std::cerr, tm_));
}
for (unsigned i = 1, e = p2vMap_.size(); i != e; ++i)