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[mips] Add ISA_<name> adverbs and start using them instead of AdditionalPredicates overrides

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Summary:
One small functional change. The recently added PAUSE instruction now has
the HasStdEnc predicate which was accidentally removed by a Requires<>.

Depends on D3640

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3641

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208209 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2014-05-07 13:57:22 +00:00
parent 2842c051b3
commit b1c5f88237
4 changed files with 46 additions and 42 deletions
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3
lib/Target/Mips/Mips.td
View File

@ -26,11 +26,14 @@ class PredicateControl {
list<Predicate> GPRPredicates = [];
// Predicates for the FGR size and layout such as IsFP64bit
list<Predicate> FGRPredicates = [];
// Predicates for the instruction group membership such as ISA's and ASE's
list<Predicate> InsnPredicates = [];
// Predicates for anything else
list<Predicate> AdditionalPredicates = [];
list<Predicate> Predicates = !listconcat(EncodingPredicates,
GPRPredicates,
FGRPredicates,
InsnPredicates,
AdditionalPredicates);
}

15
lib/Target/Mips/Mips64InstrInfo.td
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@ -118,14 +118,13 @@ def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
SRA_FM<0x3f, 0>;
// Rotate Instructions
let AdditionalPredicates = [HasMips64r2] in {
def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
immZExt6>, SRA_FM<0x3a, 1>;
def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
SRLV_FM<0x16, 1>;
def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
SRA_FM<0x3e, 1>;
}
def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
immZExt6>,
SRA_FM<0x3a, 1>, ISA_MIPS64R2;
def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
SRLV_FM<0x16, 1>, ISA_MIPS64R2;
def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
SRA_FM<0x3e, 1>, ISA_MIPS64R2;
/// Load and Store Instructions
/// aligned

41
lib/Target/Mips/MipsInstrFPU.td
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@ -429,51 +429,48 @@ def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
ADDS_FM<0x01, 16>;
defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
let AdditionalPredicates = [HasMips32r2] in {
def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
MADDS_FM<4, 0>;
def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
MADDS_FM<5, 0>;
}
def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
MADDS_FM<4, 0>, ISA_MIPS32R2;
def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
MADDS_FM<5, 0>, ISA_MIPS32R2;
let AdditionalPredicates = [HasMips32r2, NoNaNsFPMath] in {
let AdditionalPredicates = [NoNaNsFPMath] in {
def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
MADDS_FM<6, 0>;
MADDS_FM<6, 0>, ISA_MIPS32R2;
def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
MADDS_FM<7, 0>;
MADDS_FM<7, 0>, ISA_MIPS32R2;
}
let FGRPredicates = [NotFP64bit],
AdditionalPredicates = [HasMips32r2] in {
let FGRPredicates = [NotFP64bit] in {
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>;
MADDS_FM<4, 1>, ISA_MIPS32R2;
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>;
MADDS_FM<5, 1>, ISA_MIPS32R2;
}
let FGRPredicates = [NotFP64bit],
AdditionalPredicates = [HasMips32r2, NoNaNsFPMath] in {
AdditionalPredicates = [NoNaNsFPMath] in {
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>;
MADDS_FM<6, 1>, ISA_MIPS32R2;
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>;
MADDS_FM<7, 1>, ISA_MIPS32R2;
}
let FGRPredicates = [IsFP64bit],
AdditionalPredicates = [HasMips32r2], isCodeGenOnly=1 in {
isCodeGenOnly=1 in {
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>;
MADDS_FM<4, 1>, ISA_MIPS32R2;
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>;
MADDS_FM<5, 1>, ISA_MIPS32R2;
}
let FGRPredicates = [IsFP64bit],
AdditionalPredicates = [HasMips32r2, NoNaNsFPMath],
AdditionalPredicates = [NoNaNsFPMath],
isCodeGenOnly=1 in {
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>;
MADDS_FM<6, 1>, ISA_MIPS32R2;
def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>;
MADDS_FM<7, 1>, ISA_MIPS32R2;
}
//===----------------------------------------------------------------------===//

29
lib/Target/Mips/MipsInstrInfo.td
View File

@ -194,6 +194,15 @@ def IsLE : Predicate<"Subtarget.isLittle()">;
def IsBE : Predicate<"!Subtarget.isLittle()">;
def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
//===----------------------------------------------------------------------===//
// Mips ISA membership adjectives.
//===----------------------------------------------------------------------===//
class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
//===----------------------------------------------------------------------===//
class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
let EncodingPredicates = [HasStdEnc];
}
@ -825,17 +834,14 @@ class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
!strconcat(opstr, " $rt, $rs, $pos, $size"),
[(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
FrmR, opstr> {
let AdditionalPredicates = [HasMips32r2];
}
FrmR, opstr>, ISA_MIPS32R2;
class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
SDPatternOperator Op = null_frag>:
InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
!strconcat(opstr, " $rt, $rs, $pos, $size"),
[(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
NoItinerary, FrmR, opstr> {
let AdditionalPredicates = [HasMips32r2];
NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
let Constraints = "$src = $rt";
}
@ -1000,12 +1006,11 @@ def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
SRLV_FM<7, 0>;
// Rotate Instructions
let AdditionalPredicates = [HasMips32r2] in {
def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
immZExt5>, SRA_FM<2, 1>;
def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
SRLV_FM<6, 1>;
}
def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
immZExt5>,
SRA_FM<2, 1>, ISA_MIPS32R2;
def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
SRLV_FM<6, 1>, ISA_MIPS32R2;
/// Load and Store Instructions
/// aligned
@ -1191,7 +1196,7 @@ class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
FrmOther>;
def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
def EHB : Barrier<"ehb">, BARRIER_FM<3>;
def PAUSE : Barrier<"pause">, BARRIER_FM<5>, Requires<[HasMips32r2]>;
def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
//===----------------------------------------------------------------------===//
// Instruction aliases