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X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & (C2 >> C1)) & C1. (Part of PR5039)
This tends to happen a lot with bitfield code generated by clang. A simple example for x86_64 is
uint64_t foo(uint64_t x) { return (x&1) << 42; }
which used to compile into bloated code:
shlq $42, %rdi ## encoding: [0x48,0xc1,0xe7,0x2a]
movabsq $4398046511104, %rax ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00]
andq %rdi, %rax ## encoding: [0x48,0x21,0xf8]
ret ## encoding: [0xc3]
with this patch we can fold the immediate into the and:
andq $1, %rdi ## encoding: [0x48,0x83,0xe7,0x01]
movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
shlq $42, %rax ## encoding: [0x48,0xc1,0xe0,0x2a]
ret ## encoding: [0xc3]
It's possible to save another byte by using 'andl' instead of 'andq' but I currently see no way of doing
that without making this code even more complicated. See the TODOs in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129990 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer
parent
eab631362d
commit
b20a8fc8a6
@ -1580,6 +1580,81 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
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return RetVal;
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return RetVal;
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break;
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break;
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}
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}
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR: {
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// For operations of the form (x << C1) op C2, check if we can use a smaller
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// encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
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SDValue N0 = Node->getOperand(0);
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SDValue N1 = Node->getOperand(1);
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if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
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break;
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// i8 is unshrinkable, i16 should be promoted to i32.
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if (NVT != MVT::i32 && NVT != MVT::i64)
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break;
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ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
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ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
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if (!Cst || !ShlCst)
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break;
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int64_t Val = Cst->getSExtValue();
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uint64_t ShlVal = ShlCst->getZExtValue();
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// Make sure that we don't change the operation by removing bits.
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// This only matters for OR and XOR, AND is unaffected.
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if (Opcode != ISD::AND && ((Val >> ShlVal) << ShlVal) != Val)
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break;
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unsigned ShlOp, Op;
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EVT CstVT = NVT;
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// Check the minimum bitwidth for the new constant.
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// TODO: AND32ri is the same as AND64ri32 with zext imm.
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// TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
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// TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
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if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
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CstVT = MVT::i8;
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else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
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CstVT = MVT::i32;
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// Bail if there is no smaller encoding.
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if (NVT == CstVT)
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break;
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switch (NVT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("Unsupported VT!");
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case MVT::i32:
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assert(CstVT == MVT::i8);
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ShlOp = X86::SHL32ri;
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switch (Opcode) {
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case ISD::AND: Op = X86::AND32ri8; break;
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case ISD::OR: Op = X86::OR32ri8; break;
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case ISD::XOR: Op = X86::XOR32ri8; break;
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}
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break;
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case MVT::i64:
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assert(CstVT == MVT::i8 || CstVT == MVT::i32);
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ShlOp = X86::SHL64ri;
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switch (Opcode) {
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case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
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case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
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case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
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}
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break;
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}
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// Emit the smaller op and the shift.
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SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
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SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
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return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
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getI8Imm(ShlVal));
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break;
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}
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case X86ISD::UMUL: {
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case X86ISD::UMUL: {
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SDValue N0 = Node->getOperand(0);
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SDValue N0 = Node->getOperand(0);
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SDValue N1 = Node->getOperand(1);
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SDValue N1 = Node->getOperand(1);
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101
test/CodeGen/X86/narrow-shl-cst.ll
Normal file
101
test/CodeGen/X86/narrow-shl-cst.ll
Normal file
@ -0,0 +1,101 @@
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; RUN: llc < %s -march=x86-64 | FileCheck %s
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; PR5039
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define i32 @test1(i32 %x) nounwind {
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%and = shl i32 %x, 10
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%shl = and i32 %and, 31744
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ret i32 %shl
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; CHECK: test1:
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; CHECK: andl $31
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; CHECK: shll $10
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}
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define i32 @test2(i32 %x) nounwind {
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%or = shl i32 %x, 10
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%shl = or i32 %or, 31744
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ret i32 %shl
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; CHECK: test2:
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; CHECK: orl $31
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; CHECK: shll $10
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}
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define i32 @test3(i32 %x) nounwind {
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%xor = shl i32 %x, 10
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%shl = xor i32 %xor, 31744
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ret i32 %shl
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; CHECK: test3:
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; CHECK: xorl $31
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; CHECK: shll $10
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}
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define i64 @test4(i64 %x) nounwind {
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%and = shl i64 %x, 40
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%shl = and i64 %and, 264982302294016
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ret i64 %shl
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; CHECK: test4:
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; CHECK: andq $241
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; CHECK: shlq $40
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}
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define i64 @test5(i64 %x) nounwind {
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%and = shl i64 %x, 40
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%shl = and i64 %and, 34084860461056
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ret i64 %shl
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; CHECK: test5:
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; CHECK: andq $31
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; CHECK: shlq $40
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}
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define i64 @test6(i64 %x) nounwind {
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%and = shl i64 %x, 32
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%shl = and i64 %and, -281474976710656
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ret i64 %shl
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; CHECK: test6:
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; CHECK: andq $-65536
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; CHECK: shlq $32
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}
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define i64 @test7(i64 %x) nounwind {
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%or = shl i64 %x, 40
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%shl = or i64 %or, 264982302294016
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ret i64 %shl
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; CHECK: test7:
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; CHECK: orq $241
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; CHECK: shlq $40
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}
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define i64 @test8(i64 %x) nounwind {
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%or = shl i64 %x, 40
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%shl = or i64 %or, 34084860461056
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ret i64 %shl
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; CHECK: test8:
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; CHECK: orq $31
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; CHECK: shlq $40
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}
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define i64 @test9(i64 %x) nounwind {
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%xor = shl i64 %x, 40
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%shl = xor i64 %xor, 264982302294016
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ret i64 %shl
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; CHECK: test9:
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; CHECK: orq $241
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; CHECK: shlq $40
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}
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define i64 @test10(i64 %x) nounwind {
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%xor = shl i64 %x, 40
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%shl = xor i64 %xor, 34084860461056
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ret i64 %shl
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; CHECK: test10:
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; CHECK: xorq $31
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; CHECK: shlq $40
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}
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define i64 @test11(i64 %x) nounwind {
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%xor = shl i64 %x, 33
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%shl = xor i64 %xor, -562949953421312
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ret i64 %shl
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; CHECK: test11:
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; CHECK: xorq $-65536
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; CHECK: shlq $33
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}
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