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[SystemZ] Add STOC and STOCG
These instructions are allowed to trap even if the condition is false, so for now they are only used for "*ptr = (cond ? x : *ptr)"-style constructs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187111 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford
parent
13372886a6
commit
b284e1bf08
@ -1773,22 +1773,36 @@ SystemZTargetLowering::emitSelect(MachineInstr *MI,
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// Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
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// StoreOpcode is the store to use and Invert says whether the store should
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// happen when the condition is false rather than true.
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// happen when the condition is false rather than true. If a STORE ON
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// CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
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MachineBasicBlock *
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SystemZTargetLowering::emitCondStore(MachineInstr *MI,
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MachineBasicBlock *MBB,
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unsigned StoreOpcode, bool Invert) const {
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unsigned StoreOpcode, unsigned STOCOpcode,
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bool Invert) const {
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const SystemZInstrInfo *TII = TM.getInstrInfo();
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MachineOperand Base = MI->getOperand(0);
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int64_t Disp = MI->getOperand(1).getImm();
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unsigned IndexReg = MI->getOperand(2).getReg();
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unsigned SrcReg = MI->getOperand(3).getReg();
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unsigned SrcReg = MI->getOperand(0).getReg();
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MachineOperand Base = MI->getOperand(1);
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int64_t Disp = MI->getOperand(2).getImm();
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unsigned IndexReg = MI->getOperand(3).getReg();
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unsigned CCMask = MI->getOperand(4).getImm();
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DebugLoc DL = MI->getDebugLoc();
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StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
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// Use STOCOpcode if possible. We could use different store patterns in
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// order to avoid matching the index register, but the performance trade-offs
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// might be more complicated in that case.
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if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
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if (Invert)
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CCMask = CCMask ^ SystemZ::CCMASK_ANY;
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BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
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.addReg(SrcReg).addOperand(Base).addImm(Disp).addImm(CCMask);
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MI->eraseFromParent();
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return MBB;
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}
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// Get the condition needed to branch around the store.
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if (!Invert)
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CCMask = CCMask ^ SystemZ::CCMASK_ANY;
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@ -2249,41 +2263,41 @@ EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
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return emitSelect(MI, MBB);
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case SystemZ::CondStore8_32:
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return emitCondStore(MI, MBB, SystemZ::STC32, false);
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return emitCondStore(MI, MBB, SystemZ::STC32, 0, false);
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case SystemZ::CondStore8_32Inv:
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return emitCondStore(MI, MBB, SystemZ::STC32, true);
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return emitCondStore(MI, MBB, SystemZ::STC32, 0, true);
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case SystemZ::CondStore16_32:
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return emitCondStore(MI, MBB, SystemZ::STH32, false);
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return emitCondStore(MI, MBB, SystemZ::STH32, 0, false);
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case SystemZ::CondStore16_32Inv:
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return emitCondStore(MI, MBB, SystemZ::STH32, true);
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return emitCondStore(MI, MBB, SystemZ::STH32, 0, true);
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case SystemZ::CondStore32_32:
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return emitCondStore(MI, MBB, SystemZ::ST32, false);
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return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, false);
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case SystemZ::CondStore32_32Inv:
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return emitCondStore(MI, MBB, SystemZ::ST32, true);
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return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, true);
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case SystemZ::CondStore8:
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return emitCondStore(MI, MBB, SystemZ::STC, false);
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return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
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case SystemZ::CondStore8Inv:
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return emitCondStore(MI, MBB, SystemZ::STC, true);
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return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
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case SystemZ::CondStore16:
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return emitCondStore(MI, MBB, SystemZ::STH, false);
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return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
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case SystemZ::CondStore16Inv:
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return emitCondStore(MI, MBB, SystemZ::STH, true);
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return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
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case SystemZ::CondStore32:
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return emitCondStore(MI, MBB, SystemZ::ST, false);
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return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
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case SystemZ::CondStore32Inv:
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return emitCondStore(MI, MBB, SystemZ::ST, true);
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return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
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case SystemZ::CondStore64:
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return emitCondStore(MI, MBB, SystemZ::STG, false);
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return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
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case SystemZ::CondStore64Inv:
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return emitCondStore(MI, MBB, SystemZ::STG, true);
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return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
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case SystemZ::CondStoreF32:
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return emitCondStore(MI, MBB, SystemZ::STE, false);
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return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
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case SystemZ::CondStoreF32Inv:
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return emitCondStore(MI, MBB, SystemZ::STE, true);
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return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
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case SystemZ::CondStoreF64:
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return emitCondStore(MI, MBB, SystemZ::STD, false);
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return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
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case SystemZ::CondStoreF64Inv:
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return emitCondStore(MI, MBB, SystemZ::STD, true);
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return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
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case SystemZ::AEXT128_64:
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return emitExt128(MI, MBB, false, SystemZ::subreg_low);
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@ -211,7 +211,8 @@ private:
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitCondStore(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned StoreOpcode, bool Invert) const;
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unsigned StoreOpcode, unsigned STOCOpcode,
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bool Invert) const;
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MachineBasicBlock *emitExt128(MachineInstr *MI,
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MachineBasicBlock *MBB,
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bool ClearEven, unsigned SubReg) const;
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@ -451,9 +451,11 @@ class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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// Instruction definitions with semantics
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//===----------------------------------------------------------------------===//
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//
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// These classes have the form <Category><Format>, where <Format> is one
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// These classes have the form [Cond]<Category><Format>, where <Format> is one
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// of the formats defined above and where <Category> describes the inputs
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// and outputs. <Category> can be one of:
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// and outputs. "Cond" is used if the instruction is conditional,
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// in which case the 4-bit condition-code mask is added as a final operand.
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// <Category> can be one of:
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//
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// Inherent:
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// One register output operand and no input operands.
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@ -618,6 +620,40 @@ multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
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}
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}
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class CondStoreRSY<string mnemonic, bits<16> opcode,
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RegisterOperand cls, bits<5> bytes,
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AddressingMode mode = bdaddr20only>
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: InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$R3),
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mnemonic#"$R3\t$R1, $BD2", []>,
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Requires<[FeatureLoadStoreOnCond]> {
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let mayStore = 1;
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let AccessBytes = bytes;
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}
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// Like CondStoreRSY, but used for the raw assembly form. The condition-code
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// mask is the third operand rather than being part of the mnemonic.
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class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
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RegisterOperand cls, bits<5> bytes,
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AddressingMode mode = bdaddr20only>
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: InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, uimm8zx4:$R3),
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mnemonic#"\t$R1, $BD2, $R3", []>,
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Requires<[FeatureLoadStoreOnCond]> {
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let mayStore = 1;
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let AccessBytes = bytes;
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}
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// Like CondStoreRSY, but with a fixed CC mask.
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class FixedCondStoreRSY<string mnemonic, bits<16> opcode,
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RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
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AddressingMode mode = bdaddr20only>
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: InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2),
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mnemonic#"\t$R1, $BD2", []>,
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Requires<[FeatureLoadStoreOnCond]> {
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let mayStore = 1;
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let AccessBytes = bytes;
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let R3 = ccmask;
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}
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class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
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RegisterOperand cls1, RegisterOperand cls2>
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: InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
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@ -1151,12 +1187,12 @@ class SelectWrapper<RegisterOperand cls>
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multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
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SDPatternOperator load, AddressingMode mode> {
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let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
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def "" : Pseudo<(outs), (ins mode:$addr, cls:$new, i8imm:$cc),
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def "" : Pseudo<(outs), (ins cls:$new, mode:$addr, uimm8zx4:$cc),
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[(store (z_select_ccmask cls:$new, (load mode:$addr),
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imm:$cc), mode:$addr)]>;
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def Inv : Pseudo<(outs), (ins mode:$addr, cls:$new, i8imm:$cc),
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uimm8zx4:$cc), mode:$addr)]>;
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def Inv : Pseudo<(outs), (ins cls:$new, mode:$addr, uimm8zx4:$cc),
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[(store (z_select_ccmask (load mode:$addr), cls:$new,
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imm:$cc), mode:$addr)]>;
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uimm8zx4:$cc), mode:$addr)]>;
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}
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}
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@ -107,26 +107,28 @@ defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">;
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// (integer or floating-point)
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multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
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let R1 = ccmask in {
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def "" : InstRI<0xA74, (outs), (ins brtarget16:$I2),
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"j"##name##"\t$I2", []>;
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def L : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
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def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
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"j"##name##"\t$I2", []>;
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def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
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"jg"##name##"\t$I2", []>;
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}
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def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>;
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def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
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}
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defm AsmJO : CondExtendedMnemonic<1, "o">;
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defm AsmJH : CondExtendedMnemonic<2, "h">;
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defm AsmJNLE : CondExtendedMnemonic<3, "nle">;
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defm AsmJL : CondExtendedMnemonic<4, "l">;
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defm AsmJNHE : CondExtendedMnemonic<5, "nhe">;
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defm AsmJLH : CondExtendedMnemonic<6, "lh">;
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defm AsmJNE : CondExtendedMnemonic<7, "ne">;
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defm AsmJE : CondExtendedMnemonic<8, "e">;
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defm AsmJNLH : CondExtendedMnemonic<9, "nlh">;
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defm AsmJHE : CondExtendedMnemonic<10, "he">;
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defm AsmJNL : CondExtendedMnemonic<11, "nl">;
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defm AsmJLE : CondExtendedMnemonic<12, "le">;
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defm AsmJNH : CondExtendedMnemonic<13, "nh">;
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defm AsmJNO : CondExtendedMnemonic<14, "no">;
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defm AsmO : CondExtendedMnemonic<1, "o">;
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defm AsmH : CondExtendedMnemonic<2, "h">;
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defm AsmNLE : CondExtendedMnemonic<3, "nle">;
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defm AsmL : CondExtendedMnemonic<4, "l">;
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defm AsmNHE : CondExtendedMnemonic<5, "nhe">;
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defm AsmLH : CondExtendedMnemonic<6, "lh">;
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defm AsmNE : CondExtendedMnemonic<7, "ne">;
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defm AsmE : CondExtendedMnemonic<8, "e">;
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defm AsmNLH : CondExtendedMnemonic<9, "nlh">;
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defm AsmHE : CondExtendedMnemonic<10, "he">;
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defm AsmNL : CondExtendedMnemonic<11, "nl">;
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defm AsmLE : CondExtendedMnemonic<12, "le">;
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defm AsmNH : CondExtendedMnemonic<13, "nh">;
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defm AsmNO : CondExtendedMnemonic<14, "no">;
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// Define AsmParser mnemonics for each integer condition-code mask.
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// This is like the list above, except that condition 3 is not possible
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@ -274,6 +276,17 @@ let isCodeGenOnly = 1 in
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def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
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def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
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// Store on condition.
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let isCodeGenOnly = 1, Uses = [CC] in {
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def STOC32 : CondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
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def STOC : CondStoreRSY<"stoc", 0xEBF3, GR64, 4>;
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def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
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}
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let Uses = [CC] in {
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def AsmSTOC : AsmCondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
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def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
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}
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// 8-bit immediate stores to 8-bit fields.
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defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
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@ -21,6 +21,13 @@ def FeatureDistinctOps : SystemZFeature<
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"Assume that the distinct-operands facility is installed"
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>;
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def FeatureLoadStoreOnCond : SystemZFeature<
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"load-store-on-cond", "LoadStoreOnCond",
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"Assume that the load/store-on-condition facility is installed"
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>;
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def : Processor<"z10", NoItineraries, []>;
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def : Processor<"z196", NoItineraries, [FeatureDistinctOps]>;
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def : Processor<"zEC12", NoItineraries, [FeatureDistinctOps]>;
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def : Processor<"z196", NoItineraries,
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[FeatureDistinctOps, FeatureLoadStoreOnCond]>;
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def : Processor<"zEC12", NoItineraries,
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[FeatureDistinctOps, FeatureLoadStoreOnCond]>;
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@ -21,7 +21,7 @@ SystemZSubtarget::SystemZSubtarget(const std::string &TT,
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const std::string &CPU,
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const std::string &FS)
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: SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
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TargetTriple(TT) {
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HasLoadStoreOnCond(false), TargetTriple(TT) {
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = "z10";
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@ -28,6 +28,7 @@ class StringRef;
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class SystemZSubtarget : public SystemZGenSubtargetInfo {
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protected:
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bool HasDistinctOps;
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bool HasLoadStoreOnCond;
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private:
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Triple TargetTriple;
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@ -42,6 +43,9 @@ public:
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// Return true if the target has the distinct-operands facility.
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bool hasDistinctOps() const { return HasDistinctOps; }
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// Return true if the target has the load/store-on-condition facility.
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bool hasLoadStoreOnCond() const { return HasLoadStoreOnCond; }
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// Return true if GV can be accessed using LARL for reloc model RM
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// and code model CM.
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bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,
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@ -1,6 +1,6 @@
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; Test 32-bit conditional stores that are presented as selects.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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declare void @foo(i32 *)
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@ -1,6 +1,6 @@
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; Test 64-bit conditional stores that are presented as selects.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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declare void @foo(i64 *)
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186
test/CodeGen/SystemZ/cond-store-07.ll
Normal file
186
test/CodeGen/SystemZ/cond-store-07.ll
Normal file
@ -0,0 +1,186 @@
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; Test STOCs that are presented as selects.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
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declare void @foo(i32 *)
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; Test the simple case, with the loaded value first.
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define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f1:
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; CHECK: clfi %r4, 42
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; CHECK: stocnl %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f2:
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; CHECK: clfi %r4, 42
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; CHECK: stocl %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %alt, i32 %orig
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store i32 %res, i32 *%ptr
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ret void
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}
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; Test cases where the value is explicitly sign-extended to 64 bits, with the
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; loaded value first.
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define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f3:
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; CHECK: clfi %r4, 42
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; CHECK: stocnl %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%ext = sext i32 %orig to i64
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%res = select i1 %cond, i64 %ext, i64 %alt
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%trunc = trunc i64 %res to i32
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store i32 %trunc, i32 *%ptr
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ret void
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}
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||||
|
||||
; ...and with the loaded value second
|
||||
define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: clfi %r4, 42
|
||||
; CHECK: stocl %r3, 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i32 *%ptr
|
||||
%ext = sext i32 %orig to i64
|
||||
%res = select i1 %cond, i64 %alt, i64 %ext
|
||||
%trunc = trunc i64 %res to i32
|
||||
store i32 %trunc, i32 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test cases where the value is explicitly zero-extended to 32 bits, with the
|
||||
; loaded value first.
|
||||
define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f5:
|
||||
; CHECK: clfi %r4, 42
|
||||
; CHECK: stocnl %r3, 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i32 *%ptr
|
||||
%ext = zext i32 %orig to i64
|
||||
%res = select i1 %cond, i64 %ext, i64 %alt
|
||||
%trunc = trunc i64 %res to i32
|
||||
store i32 %trunc, i32 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; ...and with the loaded value second
|
||||
define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f6:
|
||||
; CHECK: clfi %r4, 42
|
||||
; CHECK: stocl %r3, 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i32 *%ptr
|
||||
%ext = zext i32 %orig to i64
|
||||
%res = select i1 %cond, i64 %alt, i64 %ext
|
||||
%trunc = trunc i64 %res to i32
|
||||
store i32 %trunc, i32 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check the high end of the aligned STOC range.
|
||||
define void @f7(i32 *%base, i32 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f7:
|
||||
; CHECK: clfi %r4, 42
|
||||
; CHECK: stocnl %r3, 524284(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i32 *%base, i64 131071
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i32 *%ptr
|
||||
%res = select i1 %cond, i32 %orig, i32 %alt
|
||||
store i32 %res, i32 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check the next word up. Other sequences besides this one would be OK.
|
||||
define void @f8(i32 *%base, i32 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f8:
|
||||
; CHECK: agfi %r2, 524288
|
||||
; CHECK: clfi %r4, 42
|
||||
; CHECK: stocnl %r3, 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i32 *%base, i64 131072
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i32 *%ptr
|
||||
%res = select i1 %cond, i32 %orig, i32 %alt
|
||||
store i32 %res, i32 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check the low end of the STOC range.
|
||||
define void @f9(i32 *%base, i32 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f9:
|
||||
; CHECK: clfi %r4, 42
|
||||
; CHECK: stocnl %r3, -524288(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i32 *%base, i64 -131072
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i32 *%ptr
|
||||
%res = select i1 %cond, i32 %orig, i32 %alt
|
||||
store i32 %res, i32 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check the next word down, with the same comments as f8.
|
||||
define void @f10(i32 *%base, i32 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f10:
|
||||
; CHECK: agfi %r2, -524292
|
||||
; CHECK: clfi %r4, 42
|
||||
; CHECK: stocnl %r3, 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i32 *%base, i64 -131073
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i32 *%ptr
|
||||
%res = select i1 %cond, i32 %orig, i32 %alt
|
||||
store i32 %res, i32 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Try a frame index base.
|
||||
define void @f11(i32 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f11:
|
||||
; CHECK: brasl %r14, foo@PLT
|
||||
; CHECK: stocnl {{%r[0-9]+}}, {{[0-9]+}}(%r15)
|
||||
; CHECK: brasl %r14, foo@PLT
|
||||
; CHECK: br %r14
|
||||
%ptr = alloca i32
|
||||
call void @foo(i32 *%ptr)
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i32 *%ptr
|
||||
%res = select i1 %cond, i32 %orig, i32 %alt
|
||||
store i32 %res, i32 *%ptr
|
||||
call void @foo(i32 *%ptr)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test that conditionally-executed stores do not use STOC, since STOC
|
||||
; is allowed to trap even when the condition is false.
|
||||
define void @f12(i32 %a, i32 %b, i32 *%dest) {
|
||||
; CHECK-LABEL: f12:
|
||||
; CHECK-NOT: stoc
|
||||
; CHECK: br %r14
|
||||
entry:
|
||||
%cmp = icmp ule i32 %a, %b
|
||||
br i1 %cmp, label %store, label %exit
|
||||
|
||||
store:
|
||||
store i32 %b, i32 *%dest
|
||||
br label %exit
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
124
test/CodeGen/SystemZ/cond-store-08.ll
Normal file
124
test/CodeGen/SystemZ/cond-store-08.ll
Normal file
@ -0,0 +1,124 @@
|
||||
; Test STOCGs that are presented as selects.
|
||||
;
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
|
||||
|
||||
declare void @foo(i64 *)
|
||||
|
||||
; Test with the loaded value first.
|
||||
define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: clfi %r4, 42
|
||||
; CHECK: stocgnl %r3, 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i64 *%ptr
|
||||
%res = select i1 %cond, i64 %orig, i64 %alt
|
||||
store i64 %res, i64 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; ...and with the loaded value second
|
||||
define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f2:
|
||||
; CHECK: clfi %r4, 42
|
||||
; CHECK: stocgl %r3, 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i64 *%ptr
|
||||
%res = select i1 %cond, i64 %alt, i64 %orig
|
||||
store i64 %res, i64 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check the high end of the aligned STOCG range.
|
||||
define void @f3(i64 *%base, i64 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK: clfi %r4, 42
|
||||
; CHECK: stocgnl %r3, 524280(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i64 *%base, i64 65535
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i64 *%ptr
|
||||
%res = select i1 %cond, i64 %orig, i64 %alt
|
||||
store i64 %res, i64 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check the next doubleword up. Other sequences besides this one would be OK.
|
||||
define void @f4(i64 *%base, i64 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: agfi %r2, 524288
|
||||
; CHECK: clfi %r4, 42
|
||||
; CHECK: stocgnl %r3, 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i64 *%base, i64 65536
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i64 *%ptr
|
||||
%res = select i1 %cond, i64 %orig, i64 %alt
|
||||
store i64 %res, i64 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check the low end of the STOCG range.
|
||||
define void @f5(i64 *%base, i64 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f5:
|
||||
; CHECK: clfi %r4, 42
|
||||
; CHECK: stocgnl %r3, -524288(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i64 *%base, i64 -65536
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i64 *%ptr
|
||||
%res = select i1 %cond, i64 %orig, i64 %alt
|
||||
store i64 %res, i64 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check the next doubleword down, with the same comments as f4.
|
||||
define void @f6(i64 *%base, i64 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f6:
|
||||
; CHECK: agfi %r2, -524296
|
||||
; CHECK: clfi %r4, 42
|
||||
; CHECK: stocgnl %r3, 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i64 *%base, i64 -65537
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i64 *%ptr
|
||||
%res = select i1 %cond, i64 %orig, i64 %alt
|
||||
store i64 %res, i64 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Try a frame index base.
|
||||
define void @f7(i64 %alt, i32 %limit) {
|
||||
; CHECK-LABEL: f7:
|
||||
; CHECK: brasl %r14, foo@PLT
|
||||
; CHECK: stocgnl {{%r[0-9]+}}, {{[0-9]+}}(%r15)
|
||||
; CHECK: brasl %r14, foo@PLT
|
||||
; CHECK: br %r14
|
||||
%ptr = alloca i64
|
||||
call void @foo(i64 *%ptr)
|
||||
%cond = icmp ult i32 %limit, 42
|
||||
%orig = load i64 *%ptr
|
||||
%res = select i1 %cond, i64 %orig, i64 %alt
|
||||
store i64 %res, i64 *%ptr
|
||||
call void @foo(i64 *%ptr)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test that conditionally-executed stores do not use STOC, since STOC
|
||||
; is allowed to trap even when the condition is false.
|
||||
define void @f8(i64 %a, i64 %b, i64 *%dest) {
|
||||
; CHECK-LABEL: f8:
|
||||
; CHECK-NOT: stocg %r3, 0(%r4)
|
||||
; CHECK: br %r14
|
||||
entry:
|
||||
%cmp = icmp ule i64 %a, %b
|
||||
br i1 %cmp, label %store, label %exit
|
||||
|
||||
store:
|
||||
store i64 %b, i64 *%dest
|
||||
br label %exit
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
@ -6106,6 +6106,102 @@
|
||||
# CHECK: st %r15, 0
|
||||
0x50 0xf0 0x00 0x00
|
||||
|
||||
# CHECK: stoc %r1, 2(%r3), 0
|
||||
0xeb 0x10 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stoco %r1, 2(%r3)
|
||||
0xeb 0x11 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stoch %r1, 2(%r3)
|
||||
0xeb 0x12 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stocnle %r1, 2(%r3)
|
||||
0xeb 0x13 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stocl %r1, 2(%r3)
|
||||
0xeb 0x14 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stocnhe %r1, 2(%r3)
|
||||
0xeb 0x15 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stoclh %r1, 2(%r3)
|
||||
0xeb 0x16 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stocne %r1, 2(%r3)
|
||||
0xeb 0x17 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stoce %r1, 2(%r3)
|
||||
0xeb 0x18 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stocnlh %r1, 2(%r3)
|
||||
0xeb 0x19 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stoche %r1, 2(%r3)
|
||||
0xeb 0x1a 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stocnl %r1, 2(%r3)
|
||||
0xeb 0x1b 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stocle %r1, 2(%r3)
|
||||
0xeb 0x1c 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stocnh %r1, 2(%r3)
|
||||
0xeb 0x1d 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stocno %r1, 2(%r3)
|
||||
0xeb 0x1e 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stoc %r1, 2(%r3), 15
|
||||
0xeb 0x1f 0x30 0x02 0x00 0xf3
|
||||
|
||||
# CHECK: stocg %r1, 2(%r3), 0
|
||||
0xeb 0x10 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocgo %r1, 2(%r3)
|
||||
0xeb 0x11 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocgh %r1, 2(%r3)
|
||||
0xeb 0x12 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocgnle %r1, 2(%r3)
|
||||
0xeb 0x13 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocgl %r1, 2(%r3)
|
||||
0xeb 0x14 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocgnhe %r1, 2(%r3)
|
||||
0xeb 0x15 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocglh %r1, 2(%r3)
|
||||
0xeb 0x16 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocgne %r1, 2(%r3)
|
||||
0xeb 0x17 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocge %r1, 2(%r3)
|
||||
0xeb 0x18 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocgnlh %r1, 2(%r3)
|
||||
0xeb 0x19 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocghe %r1, 2(%r3)
|
||||
0xeb 0x1a 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocgnl %r1, 2(%r3)
|
||||
0xeb 0x1b 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocgle %r1, 2(%r3)
|
||||
0xeb 0x1c 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocgnh %r1, 2(%r3)
|
||||
0xeb 0x1d 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocgno %r1, 2(%r3)
|
||||
0xeb 0x1e 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stocg %r1, 2(%r3), 15
|
||||
0xeb 0x1f 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: s %r0, 0
|
||||
0x5b 0x00 0x00 0x00
|
||||
|
||||
|
||||
@ -65,3 +65,37 @@
|
||||
srlk %r0,%r0,524288
|
||||
srlk %r0,%r0,0(%r0)
|
||||
srlk %r0,%r0,0(%r1,%r2)
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stoc %r0,0,-1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stoc %r0,0,16
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stoc %r0,-524289,1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stoc %r0,524288,1
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: stoc %r0,0(%r1,%r2),1
|
||||
|
||||
stoc %r0,0,-1
|
||||
stoc %r0,0,16
|
||||
stoc %r0,-524289,1
|
||||
stoc %r0,524288,1
|
||||
stoc %r0,0(%r1,%r2),1
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stocg %r0,0,-1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stocg %r0,0,16
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stocg %r0,-524289,1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stocg %r0,524288,1
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: stocg %r0,0(%r1,%r2),1
|
||||
|
||||
stocg %r0,0,-1
|
||||
stocg %r0,0,16
|
||||
stocg %r0,-524289,1
|
||||
stocg %r0,524288,1
|
||||
stocg %r0,0(%r1,%r2),1
|
||||
|
||||
@ -295,6 +295,102 @@
|
||||
srlk %r0,%r0,524287(%r1)
|
||||
srlk %r0,%r0,524287(%r15)
|
||||
|
||||
#CHECK: stoc %r0, 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xf3]
|
||||
#CHECK: stoc %r0, 0, 15 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0xf3]
|
||||
#CHECK: stoc %r0, -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0xf3]
|
||||
#CHECK: stoc %r0, 524287, 0 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xf3]
|
||||
#CHECK: stoc %r0, 0(%r1), 0 # encoding: [0xeb,0x00,0x10,0x00,0x00,0xf3]
|
||||
#CHECK: stoc %r0, 0(%r15), 0 # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xf3]
|
||||
#CHECK: stoc %r15, 0, 0 # encoding: [0xeb,0xf0,0x00,0x00,0x00,0xf3]
|
||||
#CHECK: stoc %r1, 4095(%r2), 3 # encoding: [0xeb,0x13,0x2f,0xff,0x00,0xf3]
|
||||
|
||||
stoc %r0,0,0
|
||||
stoc %r0,0,15
|
||||
stoc %r0,-524288,0
|
||||
stoc %r0,524287,0
|
||||
stoc %r0,0(%r1),0
|
||||
stoc %r0,0(%r15),0
|
||||
stoc %r15,0,0
|
||||
stoc %r1,4095(%r2),3
|
||||
|
||||
#CHECK: stoco %r1, 2(%r3) # encoding: [0xeb,0x11,0x30,0x02,0x00,0xf3]
|
||||
#CHECK: stoch %r1, 2(%r3) # encoding: [0xeb,0x12,0x30,0x02,0x00,0xf3]
|
||||
#CHECK: stocnle %r1, 2(%r3) # encoding: [0xeb,0x13,0x30,0x02,0x00,0xf3]
|
||||
#CHECK: stocl %r1, 2(%r3) # encoding: [0xeb,0x14,0x30,0x02,0x00,0xf3]
|
||||
#CHECK: stocnhe %r1, 2(%r3) # encoding: [0xeb,0x15,0x30,0x02,0x00,0xf3]
|
||||
#CHECK: stoclh %r1, 2(%r3) # encoding: [0xeb,0x16,0x30,0x02,0x00,0xf3]
|
||||
#CHECK: stocne %r1, 2(%r3) # encoding: [0xeb,0x17,0x30,0x02,0x00,0xf3]
|
||||
#CHECK: stoce %r1, 2(%r3) # encoding: [0xeb,0x18,0x30,0x02,0x00,0xf3]
|
||||
#CHECK: stocnlh %r1, 2(%r3) # encoding: [0xeb,0x19,0x30,0x02,0x00,0xf3]
|
||||
#CHECK: stoche %r1, 2(%r3) # encoding: [0xeb,0x1a,0x30,0x02,0x00,0xf3]
|
||||
#CHECK: stocnl %r1, 2(%r3) # encoding: [0xeb,0x1b,0x30,0x02,0x00,0xf3]
|
||||
#CHECK: stocle %r1, 2(%r3) # encoding: [0xeb,0x1c,0x30,0x02,0x00,0xf3]
|
||||
#CHECK: stocnh %r1, 2(%r3) # encoding: [0xeb,0x1d,0x30,0x02,0x00,0xf3]
|
||||
#CHECK: stocno %r1, 2(%r3) # encoding: [0xeb,0x1e,0x30,0x02,0x00,0xf3]
|
||||
|
||||
stoco %r1,2(%r3)
|
||||
stoch %r1,2(%r3)
|
||||
stocnle %r1,2(%r3)
|
||||
stocl %r1,2(%r3)
|
||||
stocnhe %r1,2(%r3)
|
||||
stoclh %r1,2(%r3)
|
||||
stocne %r1,2(%r3)
|
||||
stoce %r1,2(%r3)
|
||||
stocnlh %r1,2(%r3)
|
||||
stoche %r1,2(%r3)
|
||||
stocnl %r1,2(%r3)
|
||||
stocle %r1,2(%r3)
|
||||
stocnh %r1,2(%r3)
|
||||
stocno %r1,2(%r3)
|
||||
|
||||
#CHECK: stocg %r0, 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xe3]
|
||||
#CHECK: stocg %r0, 0, 15 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0xe3]
|
||||
#CHECK: stocg %r0, -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0xe3]
|
||||
#CHECK: stocg %r0, 524287, 0 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xe3]
|
||||
#CHECK: stocg %r0, 0(%r1), 0 # encoding: [0xeb,0x00,0x10,0x00,0x00,0xe3]
|
||||
#CHECK: stocg %r0, 0(%r15), 0 # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xe3]
|
||||
#CHECK: stocg %r15, 0, 0 # encoding: [0xeb,0xf0,0x00,0x00,0x00,0xe3]
|
||||
#CHECK: stocg %r1, 4095(%r2), 3 # encoding: [0xeb,0x13,0x2f,0xff,0x00,0xe3]
|
||||
|
||||
stocg %r0,0,0
|
||||
stocg %r0,0,15
|
||||
stocg %r0,-524288,0
|
||||
stocg %r0,524287,0
|
||||
stocg %r0,0(%r1),0
|
||||
stocg %r0,0(%r15),0
|
||||
stocg %r15,0,0
|
||||
stocg %r1,4095(%r2),3
|
||||
|
||||
#CHECK: stocgo %r1, 2(%r3) # encoding: [0xeb,0x11,0x30,0x02,0x00,0xe3]
|
||||
#CHECK: stocgh %r1, 2(%r3) # encoding: [0xeb,0x12,0x30,0x02,0x00,0xe3]
|
||||
#CHECK: stocgnle %r1, 2(%r3) # encoding: [0xeb,0x13,0x30,0x02,0x00,0xe3]
|
||||
#CHECK: stocgl %r1, 2(%r3) # encoding: [0xeb,0x14,0x30,0x02,0x00,0xe3]
|
||||
#CHECK: stocgnhe %r1, 2(%r3) # encoding: [0xeb,0x15,0x30,0x02,0x00,0xe3]
|
||||
#CHECK: stocglh %r1, 2(%r3) # encoding: [0xeb,0x16,0x30,0x02,0x00,0xe3]
|
||||
#CHECK: stocgne %r1, 2(%r3) # encoding: [0xeb,0x17,0x30,0x02,0x00,0xe3]
|
||||
#CHECK: stocge %r1, 2(%r3) # encoding: [0xeb,0x18,0x30,0x02,0x00,0xe3]
|
||||
#CHECK: stocgnlh %r1, 2(%r3) # encoding: [0xeb,0x19,0x30,0x02,0x00,0xe3]
|
||||
#CHECK: stocghe %r1, 2(%r3) # encoding: [0xeb,0x1a,0x30,0x02,0x00,0xe3]
|
||||
#CHECK: stocgnl %r1, 2(%r3) # encoding: [0xeb,0x1b,0x30,0x02,0x00,0xe3]
|
||||
#CHECK: stocgle %r1, 2(%r3) # encoding: [0xeb,0x1c,0x30,0x02,0x00,0xe3]
|
||||
#CHECK: stocgnh %r1, 2(%r3) # encoding: [0xeb,0x1d,0x30,0x02,0x00,0xe3]
|
||||
#CHECK: stocgno %r1, 2(%r3) # encoding: [0xeb,0x1e,0x30,0x02,0x00,0xe3]
|
||||
|
||||
stocgo %r1,2(%r3)
|
||||
stocgh %r1,2(%r3)
|
||||
stocgnle %r1,2(%r3)
|
||||
stocgl %r1,2(%r3)
|
||||
stocgnhe %r1,2(%r3)
|
||||
stocglh %r1,2(%r3)
|
||||
stocgne %r1,2(%r3)
|
||||
stocge %r1,2(%r3)
|
||||
stocgnlh %r1,2(%r3)
|
||||
stocghe %r1,2(%r3)
|
||||
stocgnl %r1,2(%r3)
|
||||
stocgle %r1,2(%r3)
|
||||
stocgnh %r1,2(%r3)
|
||||
stocgno %r1,2(%r3)
|
||||
|
||||
#CHECK: xgrk %r0, %r0, %r0 # encoding: [0xb9,0xe7,0x00,0x00]
|
||||
#CHECK: xgrk %r0, %r0, %r15 # encoding: [0xb9,0xe7,0xf0,0x00]
|
||||
#CHECK: xgrk %r0, %r15, %r0 # encoding: [0xb9,0xe7,0x00,0x0f]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user