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More removal of std::cerr and DEBUG, replacing with DOUT instead.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31806 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2006-11-17 02:09:07 +00:00
parent 280b714cd0
commit b2b9c20b61
3 changed files with 72 additions and 65 deletions
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53
lib/CodeGen/RegAllocLocal.cpp
View File

@ -30,7 +30,6 @@
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h" #include "llvm/ADT/Statistic.h"
#include <algorithm> #include <algorithm>
#include <iostream>
using namespace llvm; using namespace llvm;
namespace { namespace {
@ -270,10 +269,10 @@ void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
assert(VirtReg && "Spilling a physical register is illegal!" assert(VirtReg && "Spilling a physical register is illegal!"
" Must not have appropriate kill for the register or use exists beyond" " Must not have appropriate kill for the register or use exists beyond"
" the intended one."); " the intended one.");
DEBUG(std::cerr << " Spilling register " << RegInfo->getName(PhysReg); DOUT << " Spilling register " << RegInfo->getName(PhysReg)
std::cerr << " containing %reg" << VirtReg; << " containing %reg" << VirtReg;
if (!isVirtRegModified(VirtReg)) if (!isVirtRegModified(VirtReg))
std::cerr << " which has not been modified, so no store necessary!"); DOUT << " which has not been modified, so no store necessary!";
// Otherwise, there is a virtual register corresponding to this physical // Otherwise, there is a virtual register corresponding to this physical
// register. We only need to spill it into its stack slot if it has been // register. We only need to spill it into its stack slot if it has been
@ -281,14 +280,14 @@ void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
if (isVirtRegModified(VirtReg)) { if (isVirtRegModified(VirtReg)) {
const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC); int FrameIndex = getStackSpaceFor(VirtReg, RC);
DEBUG(std::cerr << " to stack slot #" << FrameIndex); DOUT << " to stack slot #" << FrameIndex;
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC); RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
++NumStores; // Update statistics ++NumStores; // Update statistics
} }
getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
DEBUG(std::cerr << "\n"); DOUT << "\n";
removePhysReg(PhysReg); removePhysReg(PhysReg);
} }
@ -318,9 +317,9 @@ void RA::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
// No more use of %EAX, %AH, etc. // No more use of %EAX, %AH, etc.
// %EAX isn't dead upon definition, but %AH is. However %AH isn't // %EAX isn't dead upon definition, but %AH is. However %AH isn't
// an operand of definition MI so it's not marked as such. // an operand of definition MI so it's not marked as such.
DEBUG(std::cerr << " Register " << RegInfo->getName(*AliasSet) DOUT << " Register " << RegInfo->getName(*AliasSet)
<< " [%reg" << *AliasSet << " [%reg" << *AliasSet
<< "] is never used, removing it frame live list\n"); << "] is never used, removing it frame live list\n";
removePhysReg(*AliasSet); removePhysReg(*AliasSet);
} else } else
spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet); spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
@ -506,8 +505,8 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
DEBUG(std::cerr << " Reloading %reg" << VirtReg << " into " DOUT << " Reloading %reg" << VirtReg << " into "
<< RegInfo->getName(PhysReg) << "\n"); << RegInfo->getName(PhysReg) << "\n";
// Add move instruction(s) // Add move instruction(s)
RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC); RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
@ -526,7 +525,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
const TargetInstrInfo &TII = *TM->getInstrInfo(); const TargetInstrInfo &TII = *TM->getInstrInfo();
DEBUG(const BasicBlock *LBB = MBB.getBasicBlock(); DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
if (LBB) std::cerr << "\nStarting RegAlloc of BB: " << LBB->getName()); if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName());
// If this is the first basic block in the machine function, add live-in // If this is the first basic block in the machine function, add live-in
// registers as active. // registers as active.
@ -552,13 +551,13 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
while (MII != MBB.end()) { while (MII != MBB.end()) {
MachineInstr *MI = MII++; MachineInstr *MI = MII++;
const TargetInstrDescriptor &TID = TII.get(MI->getOpcode()); const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
DEBUG(std::cerr << "\nStarting RegAlloc of: " << *MI; DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI;
std::cerr << " Regs have values: "; DOUT << " Regs have values: ";
for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i) for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
std::cerr << "[" << RegInfo->getName(i) DOUT << "[" << RegInfo->getName(i)
<< ",%reg" << PhysRegsUsed[i] << "] "; << ",%reg" << PhysRegsUsed[i] << "] ";
std::cerr << "\n"); DOUT << "\n");
// Loop over the implicit uses, making sure that they are at the head of the // Loop over the implicit uses, making sure that they are at the head of the
// use order list, so they don't get reallocated. // use order list, so they don't get reallocated.
@ -608,15 +607,15 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
} }
if (PhysReg) { if (PhysReg) {
DEBUG(std::cerr << " Last use of " << RegInfo->getName(PhysReg) DOUT << " Last use of " << RegInfo->getName(PhysReg)
<< "[%reg" << VirtReg <<"], removing it from live set\n"); << "[%reg" << VirtReg <<"], removing it from live set\n";
removePhysReg(PhysReg); removePhysReg(PhysReg);
for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
*AliasSet; ++AliasSet) { *AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) { if (PhysRegsUsed[*AliasSet] != -2) {
DEBUG(std::cerr << " Last use of " DOUT << " Last use of "
<< RegInfo->getName(*AliasSet) << RegInfo->getName(*AliasSet)
<< "[%reg" << VirtReg <<"], removing it from live set\n"); << "[%reg" << VirtReg <<"], removing it from live set\n";
removePhysReg(*AliasSet); removePhysReg(*AliasSet);
} }
} }
@ -718,16 +717,16 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
} }
if (PhysReg) { if (PhysReg) {
DEBUG(std::cerr << " Register " << RegInfo->getName(PhysReg) DOUT << " Register " << RegInfo->getName(PhysReg)
<< " [%reg" << VirtReg << " [%reg" << VirtReg
<< "] is never used, removing it frame live list\n"); << "] is never used, removing it frame live list\n";
removePhysReg(PhysReg); removePhysReg(PhysReg);
for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
*AliasSet; ++AliasSet) { *AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) { if (PhysRegsUsed[*AliasSet] != -2) {
DEBUG(std::cerr << " Register " << RegInfo->getName(*AliasSet) DOUT << " Register " << RegInfo->getName(*AliasSet)
<< " [%reg" << *AliasSet << " [%reg" << *AliasSet
<< "] is never used, removing it frame live list\n"); << "] is never used, removing it frame live list\n";
removePhysReg(*AliasSet); removePhysReg(*AliasSet);
} }
} }
@ -775,7 +774,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
/// runOnMachineFunction - Register allocate the whole function /// runOnMachineFunction - Register allocate the whole function
/// ///
bool RA::runOnMachineFunction(MachineFunction &Fn) { bool RA::runOnMachineFunction(MachineFunction &Fn) {
DEBUG(std::cerr << "Machine Function " << "\n"); DOUT << "Machine Function " << "\n";
MF = &Fn; MF = &Fn;
TM = &Fn.getTarget(); TM = &Fn.getTarget();
RegInfo = TM->getRegisterInfo(); RegInfo = TM->getRegisterInfo();

82
lib/CodeGen/VirtRegMap.cpp
View File

@ -30,7 +30,6 @@
#include "llvm/ADT/Statistic.h" #include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include <algorithm> #include <algorithm>
#include <iostream>
using namespace llvm; using namespace llvm;
namespace { namespace {
@ -113,6 +112,11 @@ void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
} }
void VirtRegMap::print(std::ostream &OS) const { void VirtRegMap::print(std::ostream &OS) const {
llvm_ostream LOS(OS);
print(LOS);
}
void VirtRegMap::print(llvm_ostream &OS) const {
const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
OS << "********** REGISTER MAP **********\n"; OS << "********** REGISTER MAP **********\n";
@ -130,7 +134,10 @@ void VirtRegMap::print(std::ostream &OS) const {
OS << '\n'; OS << '\n';
} }
void VirtRegMap::dump() const { print(std::cerr); } void VirtRegMap::dump() const {
llvm_ostream OS = DOUT;
print(OS);
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -146,9 +153,8 @@ namespace {
} }
bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n"); DOUT << "********** REWRITE MACHINE CODE **********\n";
DEBUG(std::cerr << "********** Function: " DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
<< MF.getFunction()->getName() << '\n');
const TargetMachine &TM = MF.getTarget(); const TargetMachine &TM = MF.getTarget();
const MRegisterInfo &MRI = *TM.getRegisterInfo(); const MRegisterInfo &MRI = *TM.getRegisterInfo();
bool *PhysRegsUsed = MF.getUsedPhysregs(); bool *PhysRegsUsed = MF.getUsedPhysregs();
@ -161,7 +167,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
MBBI != E; ++MBBI) { MBBI != E; ++MBBI) {
DEBUG(std::cerr << MBBI->getBasicBlock()->getName() << ":\n"); DOUT << MBBI->getBasicBlock()->getName() << ":\n";
MachineBasicBlock &MBB = *MBBI; MachineBasicBlock &MBB = *MBBI;
for (MachineBasicBlock::iterator MII = MBB.begin(), for (MachineBasicBlock::iterator MII = MBB.begin(),
E = MBB.end(); MII != E; ++MII) { E = MBB.end(); MII != E; ++MII) {
@ -183,7 +189,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
LoadedRegs.push_back(VirtReg); LoadedRegs.push_back(VirtReg);
++NumLoads; ++NumLoads;
DEBUG(std::cerr << '\t' << *prior(MII)); DOUT << '\t' << *prior(MII);
} }
if (MO.isDef()) { if (MO.isDef()) {
@ -198,7 +204,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
} }
} }
DEBUG(std::cerr << '\t' << MI); DOUT << '\t' << MI;
LoadedRegs.clear(); LoadedRegs.clear();
} }
} }
@ -221,8 +227,8 @@ namespace {
bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
MRI = MF.getTarget().getRegisterInfo(); MRI = MF.getTarget().getRegisterInfo();
TII = MF.getTarget().getInstrInfo(); TII = MF.getTarget().getInstrInfo();
DEBUG(std::cerr << "\n**** Local spiller rewriting function '" DOUT << "\n**** Local spiller rewriting function '"
<< MF.getFunction()->getName() << "':\n"); << MF.getFunction()->getName() << "':\n";
for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
MBB != E; ++MBB) MBB != E; ++MBB)
@ -293,8 +299,8 @@ public:
PhysRegsAvailable.insert(std::make_pair(Reg, Slot)); PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
SpillSlotsAvailable[Slot] = (Reg << 1) | (unsigned)CanClobber; SpillSlotsAvailable[Slot] = (Reg << 1) | (unsigned)CanClobber;
DEBUG(std::cerr << "Remembering SS#" << Slot << " in physreg " DOUT << "Remembering SS#" << Slot << " in physreg "
<< MRI->getName(Reg) << "\n"); << MRI->getName(Reg) << "\n";
} }
/// canClobberPhysReg - Return true if the spiller is allowed to change the /// canClobberPhysReg - Return true if the spiller is allowed to change the
@ -328,8 +334,8 @@ void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg && assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
"Bidirectional map mismatch!"); "Bidirectional map mismatch!");
SpillSlotsAvailable.erase(Slot); SpillSlotsAvailable.erase(Slot);
DEBUG(std::cerr << "PhysReg " << MRI->getName(PhysReg) DOUT << "PhysReg " << MRI->getName(PhysReg)
<< " clobbered, invalidating SS#" << Slot << "\n"); << " clobbered, invalidating SS#" << Slot << "\n";
} }
} }
@ -486,9 +492,9 @@ namespace {
Spills.addAvailable(NewOp.StackSlot, NewPhysReg); Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
++NumLoads; ++NumLoads;
DEBUG(MachineBasicBlock::iterator MII = MI; DEBUG(MachineBasicBlock::iterator MII = MI;
std::cerr << '\t' << *prior(MII)); DOUT << '\t' << *prior(MII));
DEBUG(std::cerr << "Reuse undone!\n"); DOUT << "Reuse undone!\n";
--NumReused; --NumReused;
// Finally, PhysReg is now available, go ahead and use it. // Finally, PhysReg is now available, go ahead and use it.
@ -506,7 +512,7 @@ namespace {
/// register allocator is done with them. If possible, avoid reloading vregs. /// register allocator is done with them. If possible, avoid reloading vregs.
void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
DEBUG(std::cerr << MBB.getBasicBlock()->getName() << ":\n"); DOUT << MBB.getBasicBlock()->getName() << ":\n";
// Spills - Keep track of which spilled values are available in physregs so // Spills - Keep track of which spilled values are available in physregs so
// that we can choose to reuse the physregs instead of emitting reloads. // that we can choose to reuse the physregs instead of emitting reloads.
@ -600,10 +606,10 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
if (CanReuse) { if (CanReuse) {
// If this stack slot value is already available, reuse it! // If this stack slot value is already available, reuse it!
DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg " DOUT << "Reusing SS#" << StackSlot << " from physreg "
<< MRI->getName(PhysReg) << " for vreg" << MRI->getName(PhysReg) << " for vreg"
<< VirtReg <<" instead of reloading into physreg " << VirtReg <<" instead of reloading into physreg "
<< MRI->getName(VRM.getPhys(VirtReg)) << "\n"); << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
MI.getOperand(i).setReg(PhysReg); MI.getOperand(i).setReg(PhysReg);
// The only technical detail we have is that we don't know that // The only technical detail we have is that we don't know that
@ -654,10 +660,10 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
// incoming, we don't need to inserted a dead copy. // incoming, we don't need to inserted a dead copy.
if (DesignatedReg == PhysReg) { if (DesignatedReg == PhysReg) {
// If this stack slot value is already available, reuse it! // If this stack slot value is already available, reuse it!
DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg " DOUT << "Reusing SS#" << StackSlot << " from physreg "
<< MRI->getName(PhysReg) << " for vreg" << MRI->getName(PhysReg) << " for vreg"
<< VirtReg << VirtReg
<< " instead of reloading into same physreg.\n"); << " instead of reloading into same physreg.\n";
MI.getOperand(i).setReg(PhysReg); MI.getOperand(i).setReg(PhysReg);
ReusedOperands.markClobbered(PhysReg); ReusedOperands.markClobbered(PhysReg);
++NumReused; ++NumReused;
@ -676,7 +682,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Spills.addAvailable(StackSlot, DesignatedReg); Spills.addAvailable(StackSlot, DesignatedReg);
MI.getOperand(i).setReg(DesignatedReg); MI.getOperand(i).setReg(DesignatedReg);
DEBUG(std::cerr << '\t' << *prior(MII)); DOUT << '\t' << *prior(MII);
++NumReused; ++NumReused;
continue; continue;
} }
@ -706,26 +712,26 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Spills.addAvailable(StackSlot, PhysReg); Spills.addAvailable(StackSlot, PhysReg);
++NumLoads; ++NumLoads;
MI.getOperand(i).setReg(PhysReg); MI.getOperand(i).setReg(PhysReg);
DEBUG(std::cerr << '\t' << *prior(MII)); DOUT << '\t' << *prior(MII);
} }
DEBUG(std::cerr << '\t' << MI); DOUT << '\t' << MI;
// If we have folded references to memory operands, make sure we clear all // If we have folded references to memory operands, make sure we clear all
// physical registers that may contain the value of the spilled virtual // physical registers that may contain the value of the spilled virtual
// register // register
VirtRegMap::MI2VirtMapTy::const_iterator I, End; VirtRegMap::MI2VirtMapTy::const_iterator I, End;
for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
DEBUG(std::cerr << "Folded vreg: " << I->second.first << " MR: " DOUT << "Folded vreg: " << I->second.first << " MR: "
<< I->second.second); << I->second.second;
unsigned VirtReg = I->second.first; unsigned VirtReg = I->second.first;
VirtRegMap::ModRef MR = I->second.second; VirtRegMap::ModRef MR = I->second.second;
if (!VRM.hasStackSlot(VirtReg)) { if (!VRM.hasStackSlot(VirtReg)) {
DEBUG(std::cerr << ": No stack slot!\n"); DOUT << ": No stack slot!\n";
continue; continue;
} }
int SS = VRM.getStackSlot(VirtReg); int SS = VRM.getStackSlot(VirtReg);
DEBUG(std::cerr << " - StackSlot: " << SS << "\n"); DOUT << " - StackSlot: " << SS << "\n";
// If this folded instruction is just a use, check to see if it's a // If this folded instruction is just a use, check to see if it's a
// straight load from the virt reg slot. // straight load from the virt reg slot.
@ -736,7 +742,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
// If this spill slot is available, turn it into a copy (or nothing) // If this spill slot is available, turn it into a copy (or nothing)
// instead of leaving it as a load! // instead of leaving it as a load!
if (unsigned InReg = Spills.getSpillSlotPhysReg(SS)) { if (unsigned InReg = Spills.getSpillSlotPhysReg(SS)) {
DEBUG(std::cerr << "Promoted Load To Copy: " << MI); DOUT << "Promoted Load To Copy: " << MI;
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
if (DestReg != InReg) { if (DestReg != InReg) {
MRI->copyRegToReg(MBB, &MI, DestReg, InReg, MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
@ -764,7 +770,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
else { else {
// If we get here, the store is dead, nuke it now. // If we get here, the store is dead, nuke it now.
assert(VirtRegMap::isMod && "Can't be modref!"); assert(VirtRegMap::isMod && "Can't be modref!");
DEBUG(std::cerr << "Removed dead store:\t" << *MDSI->second); DOUT << "Removed dead store:\t" << *MDSI->second;
MBB.erase(MDSI->second); MBB.erase(MDSI->second);
VRM.RemoveFromFoldedVirtMap(MDSI->second); VRM.RemoveFromFoldedVirtMap(MDSI->second);
MaybeDeadStores.erase(MDSI); MaybeDeadStores.erase(MDSI);
@ -813,7 +819,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
unsigned Src, Dst; unsigned Src, Dst;
if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
++NumDCE; ++NumDCE;
DEBUG(std::cerr << "Removing now-noop copy: " << MI); DOUT << "Removing now-noop copy: " << MI;
MBB.erase(&MI); MBB.erase(&MI);
VRM.RemoveFromFoldedVirtMap(&MI); VRM.RemoveFromFoldedVirtMap(&MI);
goto ProcessNextInst; goto ProcessNextInst;
@ -861,7 +867,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
PhysRegsUsed[PhysReg] = true; PhysRegsUsed[PhysReg] = true;
ReusedOperands.markClobbered(PhysReg); ReusedOperands.markClobbered(PhysReg);
MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
DEBUG(std::cerr << "Store:\t" << *next(MII)); DOUT << "Store:\t" << *next(MII);
MI.getOperand(i).setReg(PhysReg); MI.getOperand(i).setReg(PhysReg);
// Check to see if this is a noop copy. If so, eliminate the // Check to see if this is a noop copy. If so, eliminate the
@ -870,7 +876,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
unsigned Src, Dst; unsigned Src, Dst;
if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
++NumDCE; ++NumDCE;
DEBUG(std::cerr << "Removing now-noop copy: " << MI); DOUT << "Removing now-noop copy: " << MI;
MBB.erase(&MI); MBB.erase(&MI);
VRM.RemoveFromFoldedVirtMap(&MI); VRM.RemoveFromFoldedVirtMap(&MI);
goto ProcessNextInst; goto ProcessNextInst;
@ -880,7 +886,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
// If there is a dead store to this stack slot, nuke it now. // If there is a dead store to this stack slot, nuke it now.
MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
if (LastStore) { if (LastStore) {
DEBUG(std::cerr << "Removed dead store:\t" << *LastStore); DOUT << "Removed dead store:\t" << *LastStore;
++NumDSE; ++NumDSE;
MBB.erase(LastStore); MBB.erase(LastStore);
VRM.RemoveFromFoldedVirtMap(LastStore); VRM.RemoveFromFoldedVirtMap(LastStore);

2
lib/CodeGen/VirtRegMap.h
View File

@ -24,6 +24,7 @@
namespace llvm { namespace llvm {
class MachineInstr; class MachineInstr;
class TargetInstrInfo; class TargetInstrInfo;
class llvm_ostream;
class VirtRegMap { class VirtRegMap {
public: public:
@ -144,6 +145,7 @@ namespace llvm {
} }
void print(std::ostream &OS) const; void print(std::ostream &OS) const;
void print(llvm_ostream &OS) const;
void dump() const; void dump() const;
}; };