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[mips] Continue splitting Instruction.Predicates into smaller lists and re-join them with !listconcat
Summary: Move IsGP64bit into GPRPredicates, and IsFP64bit/NotFP64bit into FGRPredicates No functional change (confirmed by diffing tablegen-erated files). Depends on D3639 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3640 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208201 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -22,9 +22,15 @@ include "llvm/Target/Target.td"
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class PredicateControl {
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// Predicates for the encoding scheme in use such as HasStdEnc
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list<Predicate> EncodingPredicates = [];
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// Predicates for the GPR size such as IsGP64bit
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list<Predicate> GPRPredicates = [];
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// Predicates for the FGR size and layout such as IsFP64bit
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list<Predicate> FGRPredicates = [];
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// Predicates for anything else
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list<Predicate> AdditionalPredicates = [];
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list<Predicate> Predicates = !listconcat(EncodingPredicates,
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GPRPredicates,
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FGRPredicates,
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AdditionalPredicates);
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}
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@ -141,14 +141,14 @@ let isCodeGenOnly = 1 in
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def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
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CMov_I_F_FM<19, 16>, AdditionalRequires<[IsGP64bit]>;
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let AdditionalPredicates = [NotFP64bit] in {
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let FGRPredicates = [NotFP64bit] in {
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def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
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II_MOVZ_D>, CMov_I_F_FM<18, 17>;
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def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
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II_MOVN_D>, CMov_I_F_FM<19, 17>;
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}
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let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
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CMov_I_F_FM<18, 17>;
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def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
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@ -180,14 +180,14 @@ def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
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def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
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CMov_F_F_FM<16, 0>;
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let AdditionalPredicates = [NotFP64bit] in {
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let FGRPredicates = [NotFP64bit] in {
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def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
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MipsCMovFP_T>, CMov_F_F_FM<17, 1>;
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def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
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MipsCMovFP_F>, CMov_F_F_FM<17, 0>;
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}
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let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
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CMov_F_F_FM<17, 1>;
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def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
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@ -198,7 +198,7 @@ let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>;
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defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>;
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let AdditionalPredicates = [IsGP64bit] in {
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let GPRPredicates = [IsGP64bit] in {
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defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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@ -213,7 +213,7 @@ let AdditionalPredicates = [IsGP64bit] in {
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}
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defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>;
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let AdditionalPredicates = [IsGP64bit] in {
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let GPRPredicates = [IsGP64bit] in {
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defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>;
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defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>;
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defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>;
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@ -222,19 +222,18 @@ let AdditionalPredicates = [IsGP64bit] in {
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defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>;
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defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>;
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let AdditionalPredicates = [IsGP64bit] in {
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defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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let GPRPredicates = [IsGP64bit] in {
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defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>;
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defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>;
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defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>;
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}
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let AdditionalPredicates = [NotFP64bit] in {
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let FGRPredicates = [NotFP64bit] in {
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defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>;
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defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>;
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}
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let AdditionalPredicates = [IsFP64bit] in {
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let FGRPredicates = [IsFP64bit] in {
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defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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@ -266,7 +266,7 @@ defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>;
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defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>;
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defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
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let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
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ABSS_FM<0x8, 16>;
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def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
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@ -292,7 +292,7 @@ def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
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def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
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ABSS_FM<0x25, 17>;
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let AdditionalPredicates = [NotFP64bit] in {
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let FGRPredicates = [NotFP64bit] in {
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def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
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ABSS_FM<0x20, 17>;
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def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
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@ -301,7 +301,7 @@ let AdditionalPredicates = [NotFP64bit] in {
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ABSS_FM<0x21, 16>;
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}
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let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
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ABSS_FM<0x20, 17>;
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def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
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@ -367,12 +367,12 @@ def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
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def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>;
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def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
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let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>;
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def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>;
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}
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let AdditionalPredicates = [NotFP64bit] in {
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let FGRPredicates = [NotFP64bit] in {
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def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>;
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def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>;
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}
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@ -391,25 +391,26 @@ let AdditionalPredicates = [IsNotNaCl, HasFPIdx] in {
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def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>;
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}
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let AdditionalPredicates = [NotFP64bit, HasFPIdx, NotInMicroMips,
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IsNotNaCl] in {
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let FGRPredicates = [NotFP64bit],
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AdditionalPredicates = [HasFPIdx, NotInMicroMips, IsNotNaCl] in {
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def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>;
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def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>;
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}
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let AdditionalPredicates = [IsFP64bit, HasFPIdx],
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let FGRPredicates = [IsFP64bit], AdditionalPredicates = [HasFPIdx],
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DecoderNamespace="Mips64" in {
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def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>;
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def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>;
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}
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// Load/store doubleword indexed unaligned.
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let AdditionalPredicates = [NotFP64bit, IsNotNaCl] in {
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let FGRPredicates = [NotFP64bit],
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AdditionalPredicates = [IsNotNaCl] in {
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def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>;
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def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>;
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}
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let AdditionalPredicates = [IsFP64bit], DecoderNamespace="Mips64" in {
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let FGRPredicates = [IsFP64bit], DecoderNamespace="Mips64" in {
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def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>;
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def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>;
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}
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@ -442,28 +443,32 @@ let AdditionalPredicates = [HasMips32r2, NoNaNsFPMath] in {
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MADDS_FM<7, 0>;
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}
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let AdditionalPredicates = [NotFP64bit, HasMips32r2] in {
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let FGRPredicates = [NotFP64bit],
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AdditionalPredicates = [HasMips32r2] in {
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def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
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MADDS_FM<4, 1>;
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def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
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MADDS_FM<5, 1>;
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}
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let AdditionalPredicates = [NotFP64bit, HasMips32r2, NoNaNsFPMath] in {
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let FGRPredicates = [NotFP64bit],
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AdditionalPredicates = [HasMips32r2, NoNaNsFPMath] in {
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def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
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MADDS_FM<6, 1>;
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def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
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MADDS_FM<7, 1>;
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}
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let AdditionalPredicates = [IsFP64bit, HasMips32r2], isCodeGenOnly=1 in {
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let FGRPredicates = [IsFP64bit],
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AdditionalPredicates = [HasMips32r2], isCodeGenOnly=1 in {
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def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
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MADDS_FM<4, 1>;
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def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
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MADDS_FM<5, 1>;
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}
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let AdditionalPredicates = [IsFP64bit, HasMips32r2, NoNaNsFPMath],
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let FGRPredicates = [IsFP64bit],
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AdditionalPredicates = [HasMips32r2, NoNaNsFPMath],
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isCodeGenOnly=1 in {
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def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
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MADDS_FM<6, 1>;
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@ -559,7 +564,7 @@ def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
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def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
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(TRUNC_W_S FGR32Opnd:$src)>;
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let AdditionalPredicates = [NotFP64bit] in {
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let FGRPredicates = [NotFP64bit] in {
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def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
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(PseudoCVT_D32_W GPR32Opnd:$src)>;
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def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
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@ -570,7 +575,7 @@ let AdditionalPredicates = [NotFP64bit] in {
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(CVT_D32_S FGR32Opnd:$src)>;
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}
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let AdditionalPredicates = [IsFP64bit] in {
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let FGRPredicates = [IsFP64bit] in {
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def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
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def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
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@ -599,12 +604,12 @@ let AddedComplexity = 40 in {
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def : LoadRegImmPat<LWC1, f32, load>;
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def : StoreRegImmPat<SWC1, f32>;
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let AdditionalPredicates = [IsFP64bit] in {
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let FGRPredicates = [IsFP64bit] in {
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def : LoadRegImmPat<LDC164, f64, load>;
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def : StoreRegImmPat<SDC164, f64>;
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}
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let AdditionalPredicates = [NotFP64bit] in {
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let FGRPredicates = [NotFP64bit] in {
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def : LoadRegImmPat<LDC1, f64, load>;
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def : StoreRegImmPat<SDC1, f64>;
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}
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