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[SystemZ] Fix FPR dwarf numbering

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The dwarf FPR numbers are supposed to have the order F0, F2, F4, F6,
F1, F3, F5, F7, F8, etc., which matches the pairing of registers for
long doubles.  E.g. a long double stored in F0 is paired with F2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212701 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2014-07-10 10:45:11 +00:00
parent b0b3161567
commit b350ec7ec6
2 changed files with 62 additions and 14 deletions
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25
lib/Target/SystemZ/SystemZRegisterInfo.td
View File

@ -119,6 +119,29 @@ defm ADDR128 : SystemZRegClass<"ADDR128", untyped, 128, (sub GR128Bit, R0Q)>;
// Floating-point registers
//===----------------------------------------------------------------------===//
// Maps FPR register numbers to their DWARF encoding.
class DwarfMapping<int id> { int Id = id; }
def F0Dwarf : DwarfMapping<16>;
def F2Dwarf : DwarfMapping<17>;
def F4Dwarf : DwarfMapping<18>;
def F6Dwarf : DwarfMapping<19>;
def F1Dwarf : DwarfMapping<20>;
def F3Dwarf : DwarfMapping<21>;
def F5Dwarf : DwarfMapping<22>;
def F7Dwarf : DwarfMapping<23>;
def F8Dwarf : DwarfMapping<24>;
def F10Dwarf : DwarfMapping<25>;
def F12Dwarf : DwarfMapping<26>;
def F14Dwarf : DwarfMapping<27>;
def F9Dwarf : DwarfMapping<28>;
def F11Dwarf : DwarfMapping<29>;
def F13Dwarf : DwarfMapping<30>;
def F15Dwarf : DwarfMapping<31>;
// Lower 32 bits of one of the 16 64-bit floating-point registers
class FPR32<bits<16> num, string n> : SystemZReg<n> {
let HWEncoding = num;
@ -142,7 +165,7 @@ class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
foreach I = 0-15 in {
def F#I#S : FPR32<I, "f"#I>;
def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
DwarfRegNum<[!add(I, 16)]>;
DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
}
foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in {

51
test/DebugInfo/SystemZ/eh_frame.s
View File

@ -11,9 +11,25 @@ check_largest_class:
.cfi_offset %r13, -56
.cfi_offset %r14, -48
.cfi_offset %r15, -40
aghi %r15, -160
.cfi_def_cfa_offset 320
lmg %r13, %r15, 264(%r15)
aghi %r15, -224
.cfi_def_cfa_offset 384
std %f8, 160(%r15)
std %f9, 168(%r15)
std %f10, 176(%r15)
std %f11, 184(%r15)
std %f12, 192(%r15)
std %f13, 200(%r15)
std %f14, 208(%r15)
std %f15, 216(%r15)
.cfi_offset %f8, -224
.cfi_offset %f9, -216
.cfi_offset %f10, -208
.cfi_offset %f11, -200
.cfi_offset %f12, -192
.cfi_offset %f13, -184
.cfi_offset %f14, -176
.cfi_offset %f15, -168
lmg %r13, %r15, 328(%r15)
br %r14
.size check_largest_class, .-check_largest_class
.cfi_endproc
@ -22,7 +38,7 @@ check_largest_class:
#
# Contents of the .eh_frame section:
#
# 00000000 0000001c 00000000 CIE
# 00000000 0000000000000014 00000000 CIE
# Version: 3
# Augmentation: "zR"
# Code alignment factor: 1
@ -35,20 +51,29 @@ check_largest_class:
# DW_CFA_nop
# DW_CFA_nop
#
# 00000020 0000001c 00000024 FDE cie=00000000 pc=00000000..00000012
# DW_CFA_advance_loc: 6 to 00000006
# 000000.. 000000000000002c 0000001c FDE cie=00000000 pc=0000000000000000..0000000000000032
# DW_CFA_advance_loc: 6 to 0000000000000006
# DW_CFA_offset: r13 at cfa-56
# DW_CFA_offset: r14 at cfa-48
# DW_CFA_offset: r15 at cfa-40
# DW_CFA_advance_loc: 4 to 0000000a
# DW_CFA_def_cfa_offset: 320
# DW_CFA_nop
# DW_CFA_advance_loc: 4 to 000000000000000a
# DW_CFA_def_cfa_offset: 384
# DW_CFA_advance_loc: 32 to 000000000000002a
# DW_CFA_offset: r24 at cfa-224
# DW_CFA_offset: r28 at cfa-216
# DW_CFA_offset: r25 at cfa-208
# DW_CFA_offset: r29 at cfa-200
# DW_CFA_offset: r26 at cfa-192
# DW_CFA_offset: r30 at cfa-184
# DW_CFA_offset: r27 at cfa-176
# DW_CFA_offset: r31 at cfa-168
# DW_CFA_nop
# DW_CFA_nop
# DW_CFA_nop
#
# CHECK: Contents of section .eh_frame:
# CHECK-NEXT: 0000 00000014 00000000 037a5200 01780e01 .........zR..x..
# CHECK-NEXT: 0010 1b0c0fa0 01000000 0000001c 0000001c ................
# CHECK-NEXT: 0020 00000000 00000012 00468d07 8e068f05 .........F......
# CHECK-NEXT: 0030 440ec002 00000000 D.......
# CHECK-NEXT: 0000 00000014 00000000 037a5200 01780e01 {{.*}}
# CHECK-NEXT: 0010 1b0c0fa0 01000000 0000002c 0000001c {{.*}}
# CHECK-NEXT: 0020 00000000 00000032 00468d07 8e068f05 {{.*}}
# CHECK-NEXT: 0030 440e8003 60981c9c 1b991a9d 199a189e {{.*}}
# CHECK-NEXT: 0040 179b169f 15000000 {{.*}}