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https://github.com/c64scene-ar/llvm-6502.git
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[AVX512] Add 512b masked integer shift by immediate patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222002 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron McInally
parent
1945dcff86
commit
b3625eb445
@ -3130,29 +3130,17 @@ def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
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// AVX-512 Shift instructions
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//===----------------------------------------------------------------------===//
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multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
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string OpcodeStr, SDNode OpNode, RegisterClass RC,
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ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
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RegisterClass KRC> {
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def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
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(ins RC:$src1, i8imm:$src2),
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!strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
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SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
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def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, i8imm:$src2),
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!strconcat(OpcodeStr,
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" \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
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[], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
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def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
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(ins x86memop:$src1, i8imm:$src2),
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!strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (OpNode (mem_frag addr:$src1),
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(i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
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def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
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(ins KRC:$mask, x86memop:$src1, i8imm:$src2),
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!strconcat(OpcodeStr,
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" \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
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[], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
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string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
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defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
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(ins _.RC:$src1, i8imm:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
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" ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
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defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
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(ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
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" ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
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}
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multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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@ -3183,42 +3171,42 @@ multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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}
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defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
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VR512, v16i32, i512mem, memopv16i32, VK16WM>,
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v16i32_info>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
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VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VQ>;
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defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
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VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
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v8i64_info>, EVEX_V512,
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EVEX_CD8<64, CD8VF>, VEX_W;
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defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
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VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
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EVEX_CD8<64, CD8VQ>, VEX_W;
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defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
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VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
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v16i32_info>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
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VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VQ>;
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defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
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VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
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v8i64_info>, EVEX_V512,
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EVEX_CD8<64, CD8VF>, VEX_W;
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defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
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VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
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EVEX_CD8<64, CD8VQ>, VEX_W;
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defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
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VR512, v16i32, i512mem, memopv16i32, VK16WM>,
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v16i32_info>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
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VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VQ>;
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defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
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VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
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v8i64_info>, EVEX_V512,
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EVEX_CD8<64, CD8VF>, VEX_W;
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defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
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VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
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@ -722,6 +722,10 @@ class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
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Requires<[HasAVX512]>;
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class AVX512BIi8Base : PD {
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Domain ExeDomain = SSEPackedInt;
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ImmType ImmT = Imm8;
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}
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class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
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@ -951,53 +951,140 @@ define <4 x double> @test_vextractf64x4(<8 x double> %a) {
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declare <4 x double> @llvm.x86.avx512.mask.vextractf64x4.512(<8 x double>, i8, <4 x double>, i8)
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define <16 x i32> @test_x86_avx512_mask_pslli_d(<16 x i32> %a0) {
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; CHECK-LABEL: test_x86_avx512_mask_pslli_d
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define <16 x i32> @test_x86_avx512_pslli_d(<16 x i32> %a0) {
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; CHECK-LABEL: test_x86_avx512_pslli_d
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; CHECK: vpslld
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%res = call <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 -1)
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ret <16 x i32> %res
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}
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define <16 x i32> @test_x86_avx512_mask_pslli_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
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; CHECK-LABEL: test_x86_avx512_mask_pslli_d
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; CHECK: vpslld $7, %zmm0, %zmm1 {%k1}
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%res = call <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)
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ret <16 x i32> %res
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}
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define <16 x i32> @test_x86_avx512_maskz_pslli_d(<16 x i32> %a0, i16 %mask) {
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; CHECK-LABEL: test_x86_avx512_maskz_pslli_d
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; CHECK: vpslld $7, %zmm0, %zmm0 {%k1} {z}
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%res = call <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 %mask)
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ret <16 x i32> %res
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}
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declare <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32>, i32, <16 x i32>, i16) nounwind readnone
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define <8 x i64> @test_x86_avx512_mask_pslli_q(<8 x i64> %a0) {
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; CHECK-LABEL: test_x86_avx512_mask_pslli_q
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define <8 x i64> @test_x86_avx512_pslli_q(<8 x i64> %a0) {
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; CHECK-LABEL: test_x86_avx512_pslli_q
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; CHECK: vpsllq
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%res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)
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ret <8 x i64> %res
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}
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define <8 x i64> @test_x86_avx512_mask_pslli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
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; CHECK-LABEL: test_x86_avx512_mask_pslli_q
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; CHECK: vpsllq $7, %zmm0, %zmm1 {%k1}
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%res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)
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ret <8 x i64> %res
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}
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define <8 x i64> @test_x86_avx512_maskz_pslli_q(<8 x i64> %a0, i8 %mask) {
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; CHECK-LABEL: test_x86_avx512_maskz_pslli_q
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; CHECK: vpsllq $7, %zmm0, %zmm0 {%k1} {z}
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%res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)
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ret <8 x i64> %res
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}
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declare <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone
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define <16 x i32> @test_x86_avx512_mask_psrli_d(<16 x i32> %a0) {
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; CHECK-LABEL: test_x86_avx512_mask_psrli_d
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define <16 x i32> @test_x86_avx512_psrli_d(<16 x i32> %a0) {
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; CHECK-LABEL: test_x86_avx512_psrli_d
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; CHECK: vpsrld
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%res = call <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 -1)
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ret <16 x i32> %res
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}
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define <16 x i32> @test_x86_avx512_mask_psrli_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
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; CHECK-LABEL: test_x86_avx512_mask_psrli_d
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; CHECK: vpsrld $7, %zmm0, %zmm1 {%k1}
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%res = call <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)
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ret <16 x i32> %res
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}
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define <16 x i32> @test_x86_avx512_maskz_psrli_d(<16 x i32> %a0, i16 %mask) {
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; CHECK-LABEL: test_x86_avx512_maskz_psrli_d
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; CHECK: vpsrld $7, %zmm0, %zmm0 {%k1} {z}
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%res = call <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 %mask)
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ret <16 x i32> %res
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}
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declare <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32>, i32, <16 x i32>, i16) nounwind readnone
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define <8 x i64> @test_x86_avx512_mask_psrli_q(<8 x i64> %a0) {
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; CHECK-LABEL: test_x86_avx512_mask_psrli_q
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define <8 x i64> @test_x86_avx512_psrli_q(<8 x i64> %a0) {
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; CHECK-LABEL: test_x86_avx512_psrli_q
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; CHECK: vpsrlq
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%res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)
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ret <8 x i64> %res
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}
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define <8 x i64> @test_x86_avx512_mask_psrli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
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; CHECK-LABEL: test_x86_avx512_mask_psrli_q
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; CHECK: vpsrlq $7, %zmm0, %zmm1 {%k1}
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%res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)
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ret <8 x i64> %res
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}
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define <8 x i64> @test_x86_avx512_maskz_psrli_q(<8 x i64> %a0, i8 %mask) {
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; CHECK-LABEL: test_x86_avx512_maskz_psrli_q
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; CHECK: vpsrlq $7, %zmm0, %zmm0 {%k1} {z}
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%res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)
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ret <8 x i64> %res
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}
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declare <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone
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define <16 x i32> @test_x86_avx512_mask_psrai_d(<16 x i32> %a0) {
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; CHECK-LABEL: test_x86_avx512_mask_psrai_d
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define <16 x i32> @test_x86_avx512_psrai_d(<16 x i32> %a0) {
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; CHECK-LABEL: test_x86_avx512_psrai_d
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; CHECK: vpsrad
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%res = call <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 -1)
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ret <16 x i32> %res
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}
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define <16 x i32> @test_x86_avx512_mask_psrai_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
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; CHECK-LABEL: test_x86_avx512_mask_psrai_d
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; CHECK: vpsrad $7, %zmm0, %zmm1 {%k1}
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%res = call <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)
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ret <16 x i32> %res
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}
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define <16 x i32> @test_x86_avx512_maskz_psrai_d(<16 x i32> %a0, i16 %mask) {
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; CHECK-LABEL: test_x86_avx512_maskz_psrai_d
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; CHECK: vpsrad $7, %zmm0, %zmm0 {%k1} {z}
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%res = call <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 %mask)
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ret <16 x i32> %res
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}
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declare <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32>, i32, <16 x i32>, i16) nounwind readnone
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define <8 x i64> @test_x86_avx512_mask_psrai_q(<8 x i64> %a0) {
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; CHECK-LABEL: test_x86_avx512_mask_psrai_q
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define <8 x i64> @test_x86_avx512_psrai_q(<8 x i64> %a0) {
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; CHECK-LABEL: test_x86_avx512_psrai_q
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; CHECK: vpsraq
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%res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)
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ret <8 x i64> %res
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}
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define <8 x i64> @test_x86_avx512_mask_psrai_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
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; CHECK-LABEL: test_x86_avx512_mask_psrai_q
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; CHECK: vpsraq $7, %zmm0, %zmm1 {%k1}
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%res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)
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ret <8 x i64> %res
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}
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define <8 x i64> @test_x86_avx512_maskz_psrai_q(<8 x i64> %a0, i8 %mask) {
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; CHECK-LABEL: test_x86_avx512_maskz_psrai_q
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; CHECK: vpsraq $7, %zmm0, %zmm0 {%k1} {z}
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%res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)
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ret <8 x i64> %res
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}
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declare <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone
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