mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Implement Neon VST[234] operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78330 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1306,11 +1306,11 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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}
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case ARMISD::VLD2D: {
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MVT VT = Op.getValueType();
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc;
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unsigned Opc = 0;
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MVT VT = Op.getValueType();
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switch (VT.getSimpleVT()) {
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default: llvm_unreachable("unhandled VLD2D type");
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case MVT::v8i8: Opc = ARM::VLD2d8; break;
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@ -1323,11 +1323,11 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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}
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case ARMISD::VLD3D: {
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MVT VT = Op.getValueType();
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc;
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unsigned Opc = 0;
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MVT VT = Op.getValueType();
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switch (VT.getSimpleVT()) {
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default: llvm_unreachable("unhandled VLD3D type");
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case MVT::v8i8: Opc = ARM::VLD3d8; break;
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@ -1340,11 +1340,11 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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}
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case ARMISD::VLD4D: {
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MVT VT = Op.getValueType();
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc;
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unsigned Opc = 0;
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MVT VT = Op.getValueType();
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switch (VT.getSimpleVT()) {
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default: llvm_unreachable("unhandled VLD4D type");
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case MVT::v8i8: Opc = ARM::VLD4d8; break;
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@ -1357,6 +1357,59 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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ResTys.push_back(MVT::Other);
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return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 3);
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}
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case ARMISD::VST2D: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc = 0;
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switch (N->getOperand(2).getValueType().getSimpleVT()) {
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default: llvm_unreachable("unhandled VST2D type");
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case MVT::v8i8: Opc = ARM::VST2d8; break;
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case MVT::v4i16: Opc = ARM::VST2d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST2d32; break;
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}
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(2), N->getOperand(3) };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 5);
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}
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case ARMISD::VST3D: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc = 0;
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switch (N->getOperand(2).getValueType().getSimpleVT()) {
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default: llvm_unreachable("unhandled VST3D type");
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case MVT::v8i8: Opc = ARM::VST3d8; break;
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case MVT::v4i16: Opc = ARM::VST3d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST3d32; break;
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}
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(2), N->getOperand(3),
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N->getOperand(4) };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
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}
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case ARMISD::VST4D: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc = 0;
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switch (N->getOperand(2).getValueType().getSimpleVT()) {
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default: llvm_unreachable("unhandled VST4D type");
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case MVT::v8i8: Opc = ARM::VST4d8; break;
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case MVT::v4i16: Opc = ARM::VST4d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST4d32; break;
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}
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(2), N->getOperand(3),
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N->getOperand(4), N->getOperand(5) };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
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}
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}
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return SelectCode(Op);
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@ -323,6 +323,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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// We want to custom lower some of our intrinsics.
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
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setOperationAction(ISD::SETCC, MVT::i32, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Expand);
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@ -466,6 +467,9 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::VLD2D: return "ARMISD::VLD2D";
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case ARMISD::VLD3D: return "ARMISD::VLD3D";
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case ARMISD::VLD4D: return "ARMISD::VLD4D";
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case ARMISD::VST2D: return "ARMISD::VST2D";
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case ARMISD::VST3D: return "ARMISD::VST3D";
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case ARMISD::VST4D: return "ARMISD::VST4D";
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}
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}
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@ -1325,6 +1329,23 @@ static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
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return DAG.getNode(Opcode, dl, Node->getVTList(), Ops, 2);
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}
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static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG,
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unsigned Opcode, unsigned NumVecs) {
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SDNode *Node = Op.getNode();
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MVT VT = Node->getOperand(3).getValueType();
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DebugLoc dl = Op.getDebugLoc();
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if (!VT.is64BitVector())
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return SDValue(); // unimplemented
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SmallVector<SDValue, 6> Ops;
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Ops.push_back(Node->getOperand(0));
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Ops.push_back(Node->getOperand(2));
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for (unsigned N = 0; N < NumVecs; ++N)
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Ops.push_back(Node->getOperand(N + 3));
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return DAG.getNode(Opcode, dl, MVT::Other, Ops.data(), Ops.size());
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}
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SDValue
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ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
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unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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@ -1340,10 +1361,13 @@ ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
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return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD4D);
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case Intrinsic::arm_neon_vst2i:
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case Intrinsic::arm_neon_vst2f:
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return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST2D, 2);
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case Intrinsic::arm_neon_vst3i:
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case Intrinsic::arm_neon_vst3f:
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return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST3D, 3);
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case Intrinsic::arm_neon_vst4i:
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case Intrinsic::arm_neon_vst4f:
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return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST4D, 4);
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default: return SDValue(); // Don't custom lower most intrinsics.
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}
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}
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@ -2381,6 +2405,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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case ISD::RETURNADDR: break;
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case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
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case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
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case ISD::INTRINSIC_VOID:
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case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
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@ -119,7 +119,10 @@ namespace llvm {
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// Vector load/store with (de)interleaving
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VLD2D,
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VLD3D,
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VLD4D
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VLD4D,
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VST2D,
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VST3D,
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VST4D
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};
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}
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@ -81,6 +81,20 @@ def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD3,
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def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD4,
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[SDNPHasChain, SDNPMayLoad]>;
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def SDTARMVST2 : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>]>;
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def SDTARMVST3 : SDTypeProfile<0, 4, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
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SDTCisSameAs<1, 3>]>;
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def SDTARMVST4 : SDTypeProfile<0, 5, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
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SDTCisSameAs<1, 3>,
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SDTCisSameAs<1, 4>]>;
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def NEONvst2d : SDNode<"ARMISD::VST2D", SDTARMVST2,
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[SDNPHasChain, SDNPMayStore]>;
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def NEONvst3d : SDNode<"ARMISD::VST3D", SDTARMVST3,
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[SDNPHasChain, SDNPMayStore]>;
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def NEONvst4d : SDNode<"ARMISD::VST4D", SDTARMVST4,
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[SDNPHasChain, SDNPMayStore]>;
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//===----------------------------------------------------------------------===//
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// NEON operand definitions
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//===----------------------------------------------------------------------===//
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@ -172,30 +186,6 @@ def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1i>;
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def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1f>;
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def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>;
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// VST1 : Vector Store (multiple single elements)
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class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
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: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
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NoItinerary,
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!strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
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[(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
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class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
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: NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
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NoItinerary,
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!strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
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[(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
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def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1i>;
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def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1i>;
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def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1i>;
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def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1f>;
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def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1i>;
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def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1i>;
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def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1i>;
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def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>;
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def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>;
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def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>;
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// VLD2 : Vector Load (multiple 2-element structures)
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class VLD2D<string OpcodeStr>
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: NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
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@ -227,6 +217,59 @@ def VLD4d8 : VLD4D<"vld4.8">;
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def VLD4d16 : VLD4D<"vld4.16">;
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def VLD4d32 : VLD4D<"vld4.32">;
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// VST1 : Vector Store (multiple single elements)
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class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
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: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
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NoItinerary,
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!strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
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[(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
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class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
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: NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
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NoItinerary,
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!strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
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[(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
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def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1i>;
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def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1i>;
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def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1i>;
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def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1f>;
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def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1i>;
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def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1i>;
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def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1i>;
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def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>;
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def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>;
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def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>;
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// VST2 : Vector Store (multiple 2-element structures)
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class VST2D<string OpcodeStr>
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: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
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!strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), []>;
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def VST2d8 : VST2D<"vst2.8">;
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def VST2d16 : VST2D<"vst2.16">;
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def VST2d32 : VST2D<"vst2.32">;
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// VST3 : Vector Store (multiple 3-element structures)
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class VST3D<string OpcodeStr>
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: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
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NoItinerary,
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!strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), []>;
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def VST3d8 : VST3D<"vst3.8">;
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def VST3d16 : VST3D<"vst3.16">;
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def VST3d32 : VST3D<"vst3.32">;
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// VST4 : Vector Store (multiple 4-element structures)
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class VST4D<string OpcodeStr>
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: NLdSt<(outs), (ins addrmode6:$addr,
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DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
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!strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), []>;
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def VST4d8 : VST4D<"vst4.8">;
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def VST4d16 : VST4D<"vst4.16">;
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def VST4d32 : VST4D<"vst4.32">;
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//===----------------------------------------------------------------------===//
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// NEON pattern fragments
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@ -62,6 +62,27 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
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FirstOpnd = 0;
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NumRegs = 4;
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return true;
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case ARM::VST2d8:
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case ARM::VST2d16:
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case ARM::VST2d32:
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FirstOpnd = 3;
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NumRegs = 2;
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return true;
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case ARM::VST3d8:
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case ARM::VST3d16:
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case ARM::VST3d32:
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FirstOpnd = 3;
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NumRegs = 3;
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return true;
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case ARM::VST4d8:
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case ARM::VST4d16:
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case ARM::VST4d32:
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FirstOpnd = 3;
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NumRegs = 4;
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return true;
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}
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return false;
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38
test/CodeGen/ARM/vst2.ll
Normal file
38
test/CodeGen/ARM/vst2.ll
Normal file
@ -0,0 +1,38 @@
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; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
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define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK: vst2i8:
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;CHECK: vst2.8
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%tmp1 = load <8 x i8>* %B
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call void @llvm.arm.neon.vst2i.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1)
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ret void
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}
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define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK: vst2i16:
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;CHECK: vst2.16
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%tmp1 = load <4 x i16>* %B
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call void @llvm.arm.neon.vst2i.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1)
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ret void
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}
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define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK: vst2i32:
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;CHECK: vst2.32
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%tmp1 = load <2 x i32>* %B
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call void @llvm.arm.neon.vst2i.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vst2f(float* %A, <2 x float>* %B) nounwind {
|
||||
;CHECK: vst2f:
|
||||
;CHECK: vst2.32
|
||||
%tmp1 = load <2 x float>* %B
|
||||
call void @llvm.arm.neon.vst2f.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.arm.neon.vst2i.v8i8(i8*, <8 x i8>, <8 x i8>) nounwind
|
||||
declare void @llvm.arm.neon.vst2i.v4i16(i8*, <4 x i16>, <4 x i16>) nounwind
|
||||
declare void @llvm.arm.neon.vst2i.v2i32(i8*, <2 x i32>, <2 x i32>) nounwind
|
||||
declare void @llvm.arm.neon.vst2f.v2f32(i8*, <2 x float>, <2 x float>) nounwind
|
38
test/CodeGen/ARM/vst3.ll
Normal file
38
test/CodeGen/ARM/vst3.ll
Normal file
@ -0,0 +1,38 @@
|
||||
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
|
||||
|
||||
define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vst3i8:
|
||||
;CHECK: vst3.8
|
||||
%tmp1 = load <8 x i8>* %B
|
||||
call void @llvm.arm.neon.vst3i.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK: vst3i16:
|
||||
;CHECK: vst3.16
|
||||
%tmp1 = load <4 x i16>* %B
|
||||
call void @llvm.arm.neon.vst3i.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind {
|
||||
;CHECK: vst3i32:
|
||||
;CHECK: vst3.32
|
||||
%tmp1 = load <2 x i32>* %B
|
||||
call void @llvm.arm.neon.vst3i.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vst3f(float* %A, <2 x float>* %B) nounwind {
|
||||
;CHECK: vst3f:
|
||||
;CHECK: vst3.32
|
||||
%tmp1 = load <2 x float>* %B
|
||||
call void @llvm.arm.neon.vst3f.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.arm.neon.vst3i.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>) nounwind
|
||||
declare void @llvm.arm.neon.vst3i.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>) nounwind
|
||||
declare void @llvm.arm.neon.vst3i.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>) nounwind
|
||||
declare void @llvm.arm.neon.vst3f.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>) nounwind
|
38
test/CodeGen/ARM/vst4.ll
Normal file
38
test/CodeGen/ARM/vst4.ll
Normal file
@ -0,0 +1,38 @@
|
||||
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
|
||||
|
||||
define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vst4i8:
|
||||
;CHECK: vst4.8
|
||||
%tmp1 = load <8 x i8>* %B
|
||||
call void @llvm.arm.neon.vst4i.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK: vst4i16:
|
||||
;CHECK: vst4.16
|
||||
%tmp1 = load <4 x i16>* %B
|
||||
call void @llvm.arm.neon.vst4i.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind {
|
||||
;CHECK: vst4i32:
|
||||
;CHECK: vst4.32
|
||||
%tmp1 = load <2 x i32>* %B
|
||||
call void @llvm.arm.neon.vst4i.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vst4f(float* %A, <2 x float>* %B) nounwind {
|
||||
;CHECK: vst4f:
|
||||
;CHECK: vst4.32
|
||||
%tmp1 = load <2 x float>* %B
|
||||
call void @llvm.arm.neon.vst4f.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.arm.neon.vst4i.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind
|
||||
declare void @llvm.arm.neon.vst4i.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) nounwind
|
||||
declare void @llvm.arm.neon.vst4i.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>) nounwind
|
||||
declare void @llvm.arm.neon.vst4f.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>) nounwind
|
Loading…
Reference in New Issue
Block a user