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https://github.com/c64scene-ar/llvm-6502.git
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Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34428 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -118,6 +118,11 @@ namespace llvm {
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return I->second;
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}
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bool hasInterval(unsigned reg) const {
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Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
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return I != r2iMap_.end();
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}
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/// getMBBStartIdx - Return the base index of the first instruction in the
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/// specified MachineBasicBlock.
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unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
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@ -189,6 +194,7 @@ namespace llvm {
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/// copies that cannot yet be coallesced into the "TryAgain" list.
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void CopyCoallesceInMBB(MachineBasicBlock *MBB,
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std::vector<CopyRec> &TryAgain);
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/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
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/// which are the src/dst of the copy instruction CopyMI. This returns true
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/// if the copy was successfully coallesced away, or if it is never possible
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@ -233,6 +239,9 @@ namespace llvm {
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LiveInterval &interval,
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unsigned SrcReg);
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/// handleLiveInRegister - Create interval for a livein register.
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void handleLiveInRegister(MachineBasicBlock* mbb, LiveInterval &interval);
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/// Return true if the two specified registers belong to different
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/// register classes. The registers may be either phys or virt regs.
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bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
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@ -241,11 +250,16 @@ namespace llvm {
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bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
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MachineInstr *CopyMI);
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bool overlapsAliases(const LiveInterval *lhs,
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const LiveInterval *rhs) const;
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/// hasRegisterUse - Returns true if there is any use of the specific
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/// reg between indexes Start and End.
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bool hasRegisterUse(unsigned Reg, unsigned Start, unsigned End);
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static LiveInterval createInterval(unsigned Reg);
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void removeInterval(unsigned Reg) {
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r2iMap_.erase(Reg);
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}
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LiveInterval &getOrCreateInterval(unsigned reg) {
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Reg2IntervalMap::iterator I = r2iMap_.find(reg);
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if (I == r2iMap_.end())
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@ -36,6 +36,7 @@
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namespace llvm {
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class MRegisterInfo;
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class BitVector;
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class LiveVariables : public MachineFunctionPass {
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public:
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@ -108,11 +109,11 @@ private:
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///
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std::vector<VarInfo> VirtRegInfo;
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/// AllocatablePhysicalRegisters - This vector keeps track of which registers
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/// are actually register allocatable by the target machine. We can not track
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/// liveness for values that are not in this set.
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/// ReservedRegisters - This vector keeps track of which registers
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/// are reserved register which are not allocatable by the target machine.
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/// We can not track liveness for values that are in this set.
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///
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BitVector AllocatablePhysicalRegisters;
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BitVector ReservedRegisters;
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private: // Intermediate data structures
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const MRegisterInfo *RegInfo;
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@ -138,11 +138,18 @@ public:
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/// is an error to add the same register to the same set more than once.
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void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); }
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/// removeLiveIn - Remove the specified register from the live in set.
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///
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void removeLiveIn(unsigned Reg);
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// Iteration support for live in sets. These sets are kept in sorted
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// order by their register number.
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typedef std::vector<unsigned>::const_iterator livein_iterator;
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livein_iterator livein_begin() const { return LiveIns.begin(); }
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livein_iterator livein_end() const { return LiveIns.end(); }
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typedef std::vector<unsigned>::iterator livein_iterator;
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typedef std::vector<unsigned>::const_iterator const_livein_iterator;
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livein_iterator livein_begin() { return LiveIns.begin(); }
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const_livein_iterator livein_begin() const { return LiveIns.begin(); }
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livein_iterator livein_end() { return LiveIns.end(); }
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const_livein_iterator livein_end() const { return LiveIns.end(); }
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bool livein_empty() const { return LiveIns.empty(); }
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// Code Layout methods.
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@ -393,6 +393,10 @@ public:
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/// the specific register or NULL if it is not found.
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MachineOperand *findRegisterUseOperand(unsigned Reg);
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/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
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/// the specific register or NULL if it is not found.
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MachineOperand *findRegisterDefOperand(unsigned Reg);
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/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
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///
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void copyKillDeadInfo(const MachineInstr *MI);
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@ -284,6 +284,17 @@ public:
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return false;
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}
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/// regsOverlap - Returns true if the two registers are equal or alias
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/// each other. The registers may be virtual register.
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bool regsOverlap(unsigned regA, unsigned regB) const {
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if (regA == regB)
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return true;
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if (isVirtualRegister(regA) || isVirtualRegister(regB))
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return false;
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return areAliases(regA, regB);
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}
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/// getCalleeSavedRegs - Return a null-terminated list of all of the
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/// callee saved registers on this target. The register should be in the
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/// order of desired callee-save stack frame offset. The first register is
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@ -295,6 +306,12 @@ public:
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/// length of this list match the getCalleeSaveRegs() list.
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virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
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/// getReservedRegs - Returns a bitset indexed by physical register number
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/// indicating if a register is a special register that has particular uses and
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/// should be considered unavailable at all times, e.g. SP, RA. This is used by
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/// register scavenger to determine what registers are free.
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virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
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//===--------------------------------------------------------------------===//
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// Register Class Information
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//
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@ -98,28 +98,6 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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// Set the MBB2IdxMap entry for this MBB.
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MBB2IdxMap[MBB->getNumber()] = MIIndex;
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// If this BB has any live ins, insert a dummy instruction at the
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// beginning of the function that we will pretend "defines" the values. This
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// is to make the interval analysis simpler by providing a number.
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if (MBB->livein_begin() != MBB->livein_end()) {
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unsigned FirstLiveIn = *MBB->livein_begin();
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// Find a reg class that contains this live in.
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const TargetRegisterClass *RC = 0;
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for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
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RCE = mri_->regclass_end(); RCI != RCE; ++RCI)
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if ((*RCI)->contains(FirstLiveIn)) {
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RC = *RCI;
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break;
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}
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MachineInstr *OldFirstMI = MBB->begin();
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mri_->copyRegToReg(*MBB, MBB->begin(),
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FirstLiveIn, FirstLiveIn, RC);
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assert(OldFirstMI != MBB->begin() &&
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"copyRetToReg didn't insert anything!");
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}
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I) {
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bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
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@ -161,7 +139,17 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
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(RegRep = rep(srcReg)) == rep(dstReg)) {
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// remove from def list
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getOrCreateInterval(RegRep);
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LiveInterval &RegInt = getOrCreateInterval(RegRep);
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MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
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// If def of this move instruction is dead, remove its live range from
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// the dstination register's live interval.
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if (MO->isDead()) {
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unsigned MoveIdx = getDefIndex(getInstructionIndex(mii));
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LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx);
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RegInt.removeRange(MLR->start, MoveIdx+1);
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if (RegInt.empty())
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removeInterval(RegRep);
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}
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RemoveMachineInstrFromMaps(mii);
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mii = mbbi->erase(mii);
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++numPeep;
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@ -185,7 +173,6 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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}
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}
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for (iterator I = begin(), E = end(); I != E; ++I) {
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LiveInterval &LI = I->second;
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if (MRegisterInfo::isVirtualRegister(LI.reg)) {
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@ -670,6 +657,43 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
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}
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}
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void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
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LiveInterval &interval) {
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DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
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// Look for kills, if it reaches a def before it's killed, then it shouldn't
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// be considered a livein.
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MachineBasicBlock::iterator mi = MBB->begin();
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unsigned baseIndex = 0;
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unsigned start = 0;
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unsigned end = start;
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while (mi != MBB->end()) {
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if (lv_->KillsRegister(mi, interval.reg)) {
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DOUT << " killed";
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end = getUseIndex(baseIndex) + 1;
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goto exit;
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} else if (lv_->ModifiesRegister(mi, interval.reg)) {
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// Another instruction redefines the register before it is ever read.
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// Then the register is essentially dead at the instruction that defines
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// it. Hence its interval is:
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// [defSlot(def), defSlot(def)+1)
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DOUT << " dead";
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end = getDefIndex(start) + 1;
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goto exit;
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}
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baseIndex += InstrSlots::NUM;
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++mi;
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}
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exit:
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assert(start < end && "did not find end of interval?");
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LiveRange LR(start, end, interval.getNextValue(~0U, 0));
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interval.addRange(LR);
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DOUT << " +" << LR << '\n';
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}
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/// computeIntervals - computes the live intervals for virtual
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/// registers. for some ordering of the machine instructions [1,N] a
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/// live interval is an interval [i, j) where 1 <= i <= j < N for
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@ -688,17 +712,13 @@ void LiveIntervals::computeIntervals() {
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MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
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if (MBB->livein_begin() != MBB->livein_end()) {
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// Process live-ins to this BB first.
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for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
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// Create intervals for live-ins to this BB first.
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for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
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LE = MBB->livein_end(); LI != LE; ++LI) {
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handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex,
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getOrCreateInterval(*LI), 0);
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handleLiveInRegister(MBB, getOrCreateInterval(*LI));
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for (const unsigned* AS = mri_->getAliasSet(*LI); *AS; ++AS)
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handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex,
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getOrCreateInterval(*AS), 0);
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handleLiveInRegister(MBB, getOrCreateInterval(*AS));
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}
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++MI;
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MIIndex += InstrSlots::NUM;
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}
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for (; MI != miEnd; ++MI) {
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@ -815,7 +835,6 @@ bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
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return true;
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}
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/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
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/// which are the src/dst of the copy instruction CopyMI. This returns true
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/// if the copy was successfully coallesced away, or if it is never possible
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@ -825,54 +844,93 @@ bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
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bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
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unsigned SrcReg, unsigned DstReg) {
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DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI;
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// Get representative registers.
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SrcReg = rep(SrcReg);
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DstReg = rep(DstReg);
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unsigned repSrcReg = rep(SrcReg);
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unsigned repDstReg = rep(DstReg);
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// If they are already joined we continue.
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if (SrcReg == DstReg) {
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if (repSrcReg == repDstReg) {
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DOUT << "\tCopy already coallesced.\n";
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return true; // Not coallescable.
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}
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// If they are both physical registers, we cannot join them.
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if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
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MRegisterInfo::isPhysicalRegister(DstReg)) {
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if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
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MRegisterInfo::isPhysicalRegister(repDstReg)) {
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DOUT << "\tCan not coallesce physregs.\n";
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return true; // Not coallescable.
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}
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// We only join virtual registers with allocatable physical registers.
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if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){
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if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
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!allocatableRegs_[repSrcReg]) {
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DOUT << "\tSrc reg is unallocatable physreg.\n";
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return true; // Not coallescable.
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}
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if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){
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if (MRegisterInfo::isPhysicalRegister(repDstReg) &&
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!allocatableRegs_[repDstReg]) {
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DOUT << "\tDst reg is unallocatable physreg.\n";
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return true; // Not coallescable.
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}
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// If they are not of the same register class, we cannot join them.
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if (differingRegisterClasses(SrcReg, DstReg)) {
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if (differingRegisterClasses(repSrcReg, repDstReg)) {
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DOUT << "\tSrc/Dest are different register classes.\n";
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return true; // Not coallescable.
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}
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LiveInterval &SrcInt = getInterval(SrcReg);
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LiveInterval &DestInt = getInterval(DstReg);
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assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg &&
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LiveInterval &SrcInt = getInterval(repSrcReg);
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LiveInterval &DestInt = getInterval(repDstReg);
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assert(SrcInt.reg == repSrcReg && DestInt.reg == repDstReg &&
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"Register mapping is horribly broken!");
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DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
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DOUT << " and "; DestInt.print(DOUT, mri_);
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DOUT << ": ";
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// Check if it is necessary to propagate "isDead" property before intervals
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// are joined.
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MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
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bool isDead = mopd->isDead();
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unsigned SrcStart = 0;
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unsigned SrcEnd = 0;
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if (isDead) {
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unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
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LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx-1);
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SrcStart = SrcLR->start;
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SrcEnd = SrcLR->end;
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if (hasRegisterUse(repSrcReg, SrcStart, SrcEnd))
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isDead = false;
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}
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// Okay, attempt to join these two intervals. On failure, this returns false.
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// Otherwise, if one of the intervals being joined is a physreg, this method
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// always canonicalizes DestInt to be it. The output "SrcInt" will not have
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// been modified, so we can use this information below to update aliases.
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if (!JoinIntervals(DestInt, SrcInt)) {
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if (JoinIntervals(DestInt, SrcInt)) {
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if (isDead) {
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// Result of the copy is dead. Propagate this property.
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if (SrcStart == 0) {
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// Live-in to the function but dead. Remove it from MBB live-in set.
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// JoinIntervals may end up swapping the two intervals.
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LiveInterval &LiveInInt = (repSrcReg == DestInt.reg) ? DestInt:SrcInt;
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LiveInInt.removeRange(SrcStart, SrcEnd);
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MachineBasicBlock *MBB = CopyMI->getParent();
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MBB->removeLiveIn(SrcReg);
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} else {
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MachineInstr *SrcMI = getInstructionFromIndex(SrcStart);
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if (SrcMI) {
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// FIXME: SrcMI == NULL means the register is livein to a non-entry
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// MBB. Remove the range from its live interval?
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MachineOperand *mops = SrcMI->findRegisterDefOperand(SrcReg);
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if (mops)
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// FIXME: mops == NULL means SrcMI defines a subregister?
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mops->setIsDead();
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}
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}
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}
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} else {
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// Coallescing failed.
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// If we can eliminate the copy without merging the live ranges, do so now.
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@ -884,17 +942,17 @@ bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
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return false;
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}
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bool Swapped = SrcReg == DestInt.reg;
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bool Swapped = repSrcReg == DestInt.reg;
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if (Swapped)
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std::swap(SrcReg, DstReg);
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assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
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std::swap(repSrcReg, repDstReg);
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assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
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"LiveInterval::join didn't work right!");
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// If we're about to merge live ranges into a physical register live range,
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// we have to update any aliased register's live ranges to indicate that they
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// have clobbered values for this range.
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if (MRegisterInfo::isPhysicalRegister(DstReg)) {
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for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS)
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if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
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for (const unsigned *AS = mri_->getAliasSet(repDstReg); *AS; ++AS)
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getInterval(*AS).MergeInClobberRanges(SrcInt);
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}
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@ -904,8 +962,8 @@ bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
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// If the intervals were swapped by Join, swap them back so that the register
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// mapping (in the r2i map) is correct.
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if (Swapped) SrcInt.swap(DestInt);
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r2iMap_.erase(SrcReg);
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r2rMap_[SrcReg] = DstReg;
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removeInterval(repSrcReg);
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r2rMap_[repSrcReg] = repDstReg;
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// Finally, delete the copy instruction.
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RemoveMachineInstrFromMaps(CopyMI);
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@ -1389,6 +1447,29 @@ bool LiveIntervals::differingRegisterClasses(unsigned RegA,
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return !RegClass->contains(RegB);
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}
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/// hasRegisterUse - Returns true if there is any use of the specific
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/// reg between indexes Start and End.
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bool
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LiveIntervals::hasRegisterUse(unsigned Reg, unsigned Start, unsigned End) {
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for (unsigned Index = Start+InstrSlots::NUM; Index != End;
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Index += InstrSlots::NUM) {
|
||||
// Skip deleted instructions
|
||||
while (Index != End && !getInstructionFromIndex(Index))
|
||||
Index += InstrSlots::NUM;
|
||||
if (Index >= End) break;
|
||||
|
||||
MachineInstr *MI = getInstructionFromIndex(Index);
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isReg() && MO.isUse() && MO.getReg() &&
|
||||
mri_->regsOverlap(rep(MO.getReg()), Reg))
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
LiveInterval LiveIntervals::createInterval(unsigned reg) {
|
||||
float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
|
||||
HUGE_VALF : 0.0F;
|
||||
|
@ -71,31 +71,11 @@ LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
|
||||
return VirtRegInfo[RegIdx];
|
||||
}
|
||||
|
||||
/// registerOverlap - Returns true if register 1 is equal to register 2
|
||||
/// or if register 1 is equal to any of alias of register 2.
|
||||
static bool registerOverlap(unsigned Reg1, unsigned Reg2,
|
||||
const MRegisterInfo *RegInfo) {
|
||||
bool isVirt1 = MRegisterInfo::isVirtualRegister(Reg1);
|
||||
bool isVirt2 = MRegisterInfo::isVirtualRegister(Reg2);
|
||||
if (isVirt1 != isVirt2)
|
||||
return false;
|
||||
if (Reg1 == Reg2)
|
||||
return true;
|
||||
else if (isVirt1)
|
||||
return false;
|
||||
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg2);
|
||||
unsigned Alias = *AliasSet; ++AliasSet) {
|
||||
if (Reg1 == Alias)
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isReg() && MO.isKill()) {
|
||||
if (registerOverlap(Reg, MO.getReg(), RegInfo))
|
||||
if (RegInfo->regsOverlap(Reg, MO.getReg()))
|
||||
return true;
|
||||
}
|
||||
}
|
||||
@ -106,7 +86,7 @@ bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isReg() && MO.isDead())
|
||||
if (registerOverlap(Reg, MO.getReg(), RegInfo))
|
||||
if (RegInfo->regsOverlap(Reg, MO.getReg()))
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
@ -116,7 +96,7 @@ bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isReg() && MO.isDef()) {
|
||||
if (registerOverlap(Reg, MO.getReg(), RegInfo))
|
||||
if (RegInfo->regsOverlap(Reg, MO.getReg()))
|
||||
return true;
|
||||
}
|
||||
}
|
||||
@ -240,7 +220,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
|
||||
RegInfo = MF.getTarget().getRegisterInfo();
|
||||
assert(RegInfo && "Target doesn't have register information?");
|
||||
|
||||
AllocatablePhysicalRegisters = RegInfo->getAllocatableSet(MF);
|
||||
ReservedRegisters = RegInfo->getReservedRegs(MF);
|
||||
|
||||
// PhysRegInfo - Keep track of which instruction was the last use of a
|
||||
// physical register. This is a purely local property, because all physical
|
||||
@ -267,8 +247,8 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
|
||||
E = df_ext_end(Entry, Visited); DFI != E; ++DFI) {
|
||||
MachineBasicBlock *MBB = *DFI;
|
||||
|
||||
// Mark live-in registers as live-in.
|
||||
for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
|
||||
// Mark live-in registers as live-in.
|
||||
for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
|
||||
EE = MBB->livein_end(); II != EE; ++II) {
|
||||
assert(MRegisterInfo::isPhysicalRegister(*II) &&
|
||||
"Cannot have a live-in virtual register!");
|
||||
@ -295,7 +275,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
|
||||
if (MRegisterInfo::isVirtualRegister(MO.getReg())){
|
||||
HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
|
||||
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
|
||||
AllocatablePhysicalRegisters[MO.getReg()]) {
|
||||
!ReservedRegisters[MO.getReg()]) {
|
||||
HandlePhysRegUse(MO.getReg(), MI);
|
||||
}
|
||||
}
|
||||
@ -313,7 +293,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
|
||||
// Defaults to dead
|
||||
VRInfo.Kills.push_back(MI);
|
||||
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
|
||||
AllocatablePhysicalRegisters[MO.getReg()]) {
|
||||
!ReservedRegisters[MO.getReg()]) {
|
||||
HandlePhysRegDef(MO.getReg(), MI);
|
||||
}
|
||||
}
|
||||
|
@ -118,7 +118,7 @@ void MachineBasicBlock::print(std::ostream &OS) const {
|
||||
const MRegisterInfo *MRI = MF->getTarget().getRegisterInfo();
|
||||
if (livein_begin() != livein_end()) {
|
||||
OS << "Live Ins:";
|
||||
for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
|
||||
for (const_livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
|
||||
OutputReg(OS, *I, MRI);
|
||||
OS << "\n";
|
||||
}
|
||||
@ -144,6 +144,12 @@ void MachineBasicBlock::print(std::ostream &OS) const {
|
||||
}
|
||||
}
|
||||
|
||||
void MachineBasicBlock::removeLiveIn(unsigned Reg) {
|
||||
livein_iterator I = std::find(livein_begin(), livein_end(), Reg);
|
||||
assert(I != livein_end() && "Not a live in!");
|
||||
LiveIns.erase(I);
|
||||
}
|
||||
|
||||
void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
|
||||
MachineFunction::BasicBlockListType &BBList =getParent()->getBasicBlockList();
|
||||
getParent()->getBasicBlockList().splice(NewAfter, BBList, this);
|
||||
|
@ -180,6 +180,17 @@ MachineOperand *MachineInstr::findRegisterUseOperand(unsigned Reg) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
|
||||
/// the specific register or NULL if it is not found.
|
||||
MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
|
||||
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = getOperand(i);
|
||||
if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
|
||||
return &MO;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
|
||||
///
|
||||
void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
|
||||
|
@ -292,8 +292,9 @@ void RA::linearScan()
|
||||
}
|
||||
|
||||
// A brute force way of adding live-ins to every BB.
|
||||
for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
|
||||
MBB != E; ++MBB) {
|
||||
MachineFunction::iterator MBB = mf_->begin();
|
||||
++MBB; // Skip entry MBB.
|
||||
for (MachineFunction::iterator E = mf_->end(); MBB != E; ++MBB) {
|
||||
unsigned StartIdx = li_->getMBBStartIdx(MBB->getNumber());
|
||||
for (IntervalPtrs::iterator i = fixed_.begin(), e = fixed_.end();
|
||||
i != e; ++i)
|
||||
|
@ -28,6 +28,7 @@
|
||||
#include "llvm/Target/TargetFrameInfo.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetOptions.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include <algorithm>
|
||||
@ -297,6 +298,20 @@ ARMRegisterInfo::getCalleeSavedRegClasses() const {
|
||||
return CalleeSavedRegClasses;
|
||||
}
|
||||
|
||||
BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
||||
BitVector Reserved(getNumRegs());
|
||||
Reserved.set(ARM::SP);
|
||||
if (STI.isTargetDarwin() || hasFP(MF))
|
||||
Reserved.set(FramePtr);
|
||||
// Some targets reserve R9.
|
||||
if (STI.isR9Reserved())
|
||||
Reserved.set(ARM::R9);
|
||||
// At PEI time, if LR is used, it will be spilled upon entry.
|
||||
if (MF.getUsedPhysregs() && !MF.isPhysRegUsed((unsigned)ARM::LR))
|
||||
Reserved.set(ARM::LR);
|
||||
return Reserved;
|
||||
}
|
||||
|
||||
/// hasFP - Return true if the specified function should have a dedicated frame
|
||||
/// pointer register. This is true if the function has variable sized allocas
|
||||
/// or if frame pointer elimination is disabled.
|
||||
|
@ -67,6 +67,8 @@ public:
|
||||
|
||||
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
|
||||
|
||||
BitVector getReservedRegs(const MachineFunction &MF) const;
|
||||
|
||||
bool hasFP(const MachineFunction &MF) const;
|
||||
|
||||
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
||||
|
@ -28,6 +28,7 @@
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include <cstdlib>
|
||||
using namespace llvm;
|
||||
@ -178,6 +179,14 @@ AlphaRegisterInfo::getCalleeSavedRegClasses() const {
|
||||
return CalleeSavedRegClasses;
|
||||
}
|
||||
|
||||
BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
||||
BitVector Reserved(getNumRegs());
|
||||
Reserved.set(Alpha::R15);
|
||||
Reserved.set(Alpha::R30);
|
||||
Reserved.set(Alpha::R31);
|
||||
return Reserved;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Stack Frame Processing methods
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
@ -49,6 +49,8 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
|
||||
|
||||
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
|
||||
|
||||
BitVector getReservedRegs(const MachineFunction &MF) const;
|
||||
|
||||
bool hasFP(const MachineFunction &MF) const;
|
||||
|
||||
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
||||
|
@ -28,6 +28,7 @@
|
||||
#include "llvm/Target/TargetOptions.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
using namespace llvm;
|
||||
|
||||
@ -106,6 +107,19 @@ IA64RegisterInfo::getCalleeSavedRegClasses() const {
|
||||
return CalleeSavedRegClasses;
|
||||
}
|
||||
|
||||
BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
||||
BitVector Reserved(getNumRegs());
|
||||
Reserved.set(IA64::r0);
|
||||
Reserved.set(IA64::r1);
|
||||
Reserved.set(IA64::r2);
|
||||
Reserved.set(IA64::r5);
|
||||
Reserved.set(IA64::r12);
|
||||
Reserved.set(IA64::r13);
|
||||
Reserved.set(IA64::r22);
|
||||
Reserved.set(IA64::rp);
|
||||
return Reserved;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Stack Frame Processing methods
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
@ -48,6 +48,8 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
|
||||
|
||||
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
|
||||
|
||||
BitVector getReservedRegs(const MachineFunction &MF) const;
|
||||
|
||||
bool hasFP(const MachineFunction &MF) const;
|
||||
|
||||
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
||||
|
@ -41,7 +41,7 @@ BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
|
||||
const TargetRegisterClass *RC = *I;
|
||||
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
|
||||
E = RC->allocation_order_end(MF); I != E; ++I)
|
||||
Allocatable[*I] = true;
|
||||
Allocatable.set(*I);
|
||||
}
|
||||
return Allocatable;
|
||||
}
|
||||
|
@ -34,6 +34,7 @@
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/MathExtras.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include <cstdlib>
|
||||
using namespace llvm;
|
||||
@ -338,6 +339,35 @@ PPCRegisterInfo::getCalleeSavedRegClasses() const {
|
||||
Darwin32_CalleeSavedRegClasses;
|
||||
}
|
||||
|
||||
// needsFP - Return true if the specified function should have a dedicated frame
|
||||
// pointer register. This is true if the function has variable sized allocas or
|
||||
// if frame pointer elimination is disabled.
|
||||
//
|
||||
static bool needsFP(const MachineFunction &MF) {
|
||||
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
return NoFramePointerElim || MFI->hasVarSizedObjects();
|
||||
}
|
||||
|
||||
BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
||||
BitVector Reserved(getNumRegs());
|
||||
Reserved.set(PPC::R0);
|
||||
Reserved.set(PPC::R1);
|
||||
Reserved.set(PPC::LR);
|
||||
// In Linux, r2 is reserved for the OS.
|
||||
if (!Subtarget.isDarwin())
|
||||
Reserved.set(PPC::R2);
|
||||
// On PPC64, r13 is the thread pointer. Never allocate this register.
|
||||
// Note that this is overconservative, as it also prevents allocation of
|
||||
// R31 when the FP is not needed.
|
||||
if (Subtarget.isPPC64()) {
|
||||
Reserved.set(PPC::R13);
|
||||
Reserved.set(PPC::R31);
|
||||
}
|
||||
if (needsFP(MF))
|
||||
Reserved.set(PPC::R31);
|
||||
return Reserved;
|
||||
}
|
||||
|
||||
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
|
||||
/// copy instructions, turning them into load/store instructions.
|
||||
MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
|
||||
@ -398,15 +428,6 @@ MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
|
||||
// Stack Frame Processing methods
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// needsFP - Return true if the specified function should have a dedicated frame
|
||||
// pointer register. This is true if the function has variable sized allocas or
|
||||
// if frame pointer elimination is disabled.
|
||||
//
|
||||
static bool needsFP(const MachineFunction &MF) {
|
||||
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
return NoFramePointerElim || MFI->hasVarSizedObjects();
|
||||
}
|
||||
|
||||
// hasFP - Return true if the specified function actually has a dedicated frame
|
||||
// pointer register. This is true if the function needs a frame pointer and has
|
||||
// a non-zero stack size.
|
||||
|
@ -58,6 +58,8 @@ public:
|
||||
|
||||
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
|
||||
|
||||
BitVector getReservedRegs(const MachineFunction &MF) const;
|
||||
|
||||
/// targetHandlesStackFrameRounding - Returns true if the target is
|
||||
/// responsible for rounding up the stack frame (probably at emitPrologue
|
||||
/// time).
|
||||
|
@ -20,6 +20,7 @@
|
||||
#include "llvm/CodeGen/MachineLocation.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Type.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
using namespace llvm;
|
||||
|
||||
@ -116,6 +117,22 @@ const unsigned* SparcRegisterInfo::getCalleeSavedRegs() const {
|
||||
return CalleeSavedRegs;
|
||||
}
|
||||
|
||||
BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
||||
BitVector Reserved(getNumRegs());
|
||||
Reserved.set(SP::G2);
|
||||
Reserved.set(SP::G3);
|
||||
Reserved.set(SP::G4);
|
||||
Reserved.set(SP::O6);
|
||||
Reserved.set(SP::I6);
|
||||
Reserved.set(SP::I7);
|
||||
Reserved.set(SP::G0);
|
||||
Reserved.set(SP::G5);
|
||||
Reserved.set(SP::G6);
|
||||
Reserved.set(SP::G7);
|
||||
return Reserved;
|
||||
}
|
||||
|
||||
|
||||
const TargetRegisterClass* const*
|
||||
SparcRegisterInfo::getCalleeSavedRegClasses() const {
|
||||
static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
|
||||
|
@ -52,6 +52,8 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
|
||||
|
||||
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
|
||||
|
||||
BitVector getReservedRegs(const MachineFunction &MF) const;
|
||||
|
||||
bool hasFP(const MachineFunction &MF) const;
|
||||
|
||||
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
||||
|
@ -31,6 +31,7 @@
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetOptions.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
using namespace llvm;
|
||||
|
||||
@ -883,6 +884,21 @@ X86RegisterInfo::getCalleeSavedRegClasses() const {
|
||||
return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
|
||||
}
|
||||
|
||||
BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
||||
BitVector Reserved(getNumRegs());
|
||||
Reserved.set(X86::RSP);
|
||||
Reserved.set(X86::ESP);
|
||||
Reserved.set(X86::SP);
|
||||
Reserved.set(X86::SPL);
|
||||
if (hasFP(MF)) {
|
||||
Reserved.set(X86::RBP);
|
||||
Reserved.set(X86::EBP);
|
||||
Reserved.set(X86::BP);
|
||||
Reserved.set(X86::BPL);
|
||||
}
|
||||
return Reserved;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Stack Frame Processing methods
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
@ -78,6 +78,12 @@ public:
|
||||
/// length of this list match the getCalleeSavedRegs() list.
|
||||
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
|
||||
|
||||
/// getReservedRegs - Returns a bitset indexed by physical register number
|
||||
/// indicating if a register is a special register that has particular uses and
|
||||
/// should be considered unavailable at all times, e.g. SP, RA. This is used by
|
||||
/// register scavenger to determine what registers are free.
|
||||
BitVector getReservedRegs(const MachineFunction &MF) const;
|
||||
|
||||
bool hasFP(const MachineFunction &MF) const;
|
||||
|
||||
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
||||
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Reference in New Issue
Block a user