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[SystemZ] Use zeroing form of RISBG for some AND sequences
RISBG can handle some ANDs for which no AND IMMEDIATE exists. It also acts as a three-operand AND for some cases where an AND IMMEDIATE could be used instead. It might be worth adding a pass to replace RISBG with AND IMMEDIATE in cases where the register operands end up being the same and where AND IMMEDIATE is smaller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186072 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -33,7 +33,7 @@ define i32 @f2(i32 %orig, i8 *%ptr) {
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; register value. We can use IC but must keep the original mask.
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define i32 @f3(i32 %orig, i8 *%ptr) {
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; CHECK: f3:
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; CHECK: nill %r2, 65024
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; CHECK: risbg %r2, %r2, 32, 182, 0
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; CHECK: ic %r2, 0(%r3)
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; CHECK: br %r14
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%val = load i8 *%ptr
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@@ -46,7 +46,7 @@ define i32 @f3(i32 %orig, i8 *%ptr) {
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; Like f3, but with the operands reversed.
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define i32 @f4(i32 %orig, i8 *%ptr) {
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; CHECK: f4:
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; CHECK: nill %r2, 65024
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; CHECK: risbg %r2, %r2, 32, 182, 0
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; CHECK: ic %r2, 0(%r3)
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; CHECK: br %r14
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%val = load i8 *%ptr
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