[SystemZ] Use zeroing form of RISBG for some AND sequences

RISBG can handle some ANDs for which no AND IMMEDIATE exists.
It also acts as a three-operand AND for some cases where an
AND IMMEDIATE could be used instead.

It might be worth adding a pass to replace RISBG with AND IMMEDIATE
in cases where the register operands end up being the same and where
AND IMMEDIATE is smaller.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186072 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford
2013-07-11 08:59:12 +00:00
parent 3ee0673e4f
commit b3cabb44c3
27 changed files with 503 additions and 272 deletions

View File

@@ -33,7 +33,7 @@ define i32 @f2(i32 %orig, i8 *%ptr) {
; register value. We can use IC but must keep the original mask.
define i32 @f3(i32 %orig, i8 *%ptr) {
; CHECK: f3:
; CHECK: nill %r2, 65024
; CHECK: risbg %r2, %r2, 32, 182, 0
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
%val = load i8 *%ptr
@@ -46,7 +46,7 @@ define i32 @f3(i32 %orig, i8 *%ptr) {
; Like f3, but with the operands reversed.
define i32 @f4(i32 %orig, i8 *%ptr) {
; CHECK: f4:
; CHECK: nill %r2, 65024
; CHECK: risbg %r2, %r2, 32, 182, 0
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
%val = load i8 *%ptr