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Fix a bug in IVUsers which was permitting non-affine addrecs to
be sent to LSR, which it isn't prepared to handle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100839 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -73,8 +73,8 @@ static bool isInteresting(const SCEV *S, const Instruction *I, const Loop *L) {
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// An addrec is interesting if it's affine or if it has an interesting start.
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if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(S)) {
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// Keep things simple. Don't touch loop-variant strides.
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if (AR->getLoop() == L && (AR->isAffine() || !L->contains(I)))
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return true;
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if (AR->getLoop() == L)
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return AR->isAffine() || !L->contains(I);
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// Otherwise recurse to see if the start value is interesting.
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return isInteresting(AR->getStart(), I, L);
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}
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69
test/Transforms/LoopStrengthReduce/insert-positions.ll
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69
test/Transforms/LoopStrengthReduce/insert-positions.ll
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@ -0,0 +1,69 @@
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; RUN: llc < %s -march=x86-64 >/dev/null
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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define void @test0() nounwind {
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if.end90.i.i:
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br label %while.body.i.i221.i
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while.body.i.i221.i: ; preds = %while.cond.backedge.i.i.i, %if.end90.i.i
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br i1 undef, label %if.then.i.i224.i, label %while.cond.backedge.i.i.i
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while.cond.backedge.i.i.i: ; preds = %for.end.i.i.i, %while.body.i.i221.i
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br label %while.body.i.i221.i
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if.then.i.i224.i: ; preds = %while.body.i.i221.i
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switch i32 undef, label %for.cond.i.i226.i [
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i32 92, label %sw.bb.i.i225.i
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i32 34, label %sw.bb.i.i225.i
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i32 110, label %sw.bb21.i.i.i
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]
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sw.bb.i.i225.i: ; preds = %if.then.i.i224.i, %if.then.i.i224.i
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unreachable
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sw.bb21.i.i.i: ; preds = %if.then.i.i224.i
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unreachable
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for.cond.i.i226.i: ; preds = %for.body.i.i.i, %if.then.i.i224.i
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%0 = phi i64 [ %tmp154.i.i.i, %for.body.i.i.i ], [ 0, %if.then.i.i224.i ] ; <i64> [#uses=2]
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%tmp154.i.i.i = add i64 %0, 1 ; <i64> [#uses=2]
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%i.0.i.i.i = trunc i64 %0 to i32 ; <i32> [#uses=1]
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br i1 undef, label %land.rhs.i.i.i, label %for.end.i.i.i
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land.rhs.i.i.i: ; preds = %for.cond.i.i226.i
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br i1 undef, label %for.body.i.i.i, label %for.end.i.i.i
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for.body.i.i.i: ; preds = %land.rhs.i.i.i
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br label %for.cond.i.i226.i
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for.end.i.i.i: ; preds = %land.rhs.i.i.i, %for.cond.i.i226.i
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%idx.ext.i.i.i = sext i32 %i.0.i.i.i to i64 ; <i64> [#uses=1]
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%sub.ptr72.sum.i.i.i = xor i64 %idx.ext.i.i.i, -1 ; <i64> [#uses=1]
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%pos.addr.1.sum155.i.i.i = add i64 %tmp154.i.i.i, %sub.ptr72.sum.i.i.i ; <i64> [#uses=1]
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%arrayidx76.i.i.i = getelementptr inbounds i8* undef, i64 %pos.addr.1.sum155.i.i.i ; <i8*> [#uses=0]
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br label %while.cond.backedge.i.i.i
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}
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define void @test1() nounwind {
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entry:
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%t = shl i32 undef, undef ; <i32> [#uses=1]
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%t9 = sub nsw i32 0, %t ; <i32> [#uses=1]
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br label %outer
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outer: ; preds = %bb18, %bb
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%i12 = phi i32 [ %t21, %bb18 ], [ 0, %entry ] ; <i32> [#uses=2]
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%i13 = phi i32 [ %t20, %bb18 ], [ 0, %entry ] ; <i32> [#uses=2]
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br label %inner
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inner: ; preds = %bb16, %bb11
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%t17 = phi i32 [ %i13, %outer ], [ undef, %inner ] ; <i32> [#uses=1]
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store i32 %t17, i32* undef
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br i1 undef, label %bb18, label %inner
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bb18: ; preds = %bb16
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%t19 = add i32 %i13, %t9 ; <i32> [#uses=1]
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%t20 = add i32 %t19, %i12 ; <i32> [#uses=1]
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%t21 = add i32 %i12, 1 ; <i32> [#uses=1]
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br label %outer
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}
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