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Add support for vicmp/vfcmp codegen, more legalize support coming.

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This is necessary to unbreak the build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50988 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2008-05-12 19:40:03 +00:00
parent e4fc1ccd4d
commit b43e9c1965
6 changed files with 115 additions and 0 deletions
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8
include/llvm/CodeGen/SelectionDAG.h
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@ -346,6 +346,14 @@ public:
return getNode(ISD::SETCC, VT, LHS, RHS, getCondCode(Cond));
}
/// getVSetCC - Helper function to make it easier to build VSetCC's nodes
/// if you just have an ISD::CondCode instead of an SDOperand.
///
SDOperand getVSetCC(MVT::ValueType VT, SDOperand LHS, SDOperand RHS,
ISD::CondCode Cond) {
return getNode(ISD::VSETCC, VT, LHS, RHS, getCondCode(Cond));
}
/// getSelectCC - Helper function to make it easier to build SelectCC's if you
/// just have an ISD::CondCode instead of an SDOperand.
///

8
include/llvm/CodeGen/SelectionDAGNodes.h
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@ -332,6 +332,14 @@ namespace ISD {
// (op #2) as a CondCodeSDNode.
SETCC,
// Vector SetCC operator - This evaluates to a vector of integer elements
// with the high bit in each element set to true if the comparison is true
// and false if the comparison is false. All other bits in each element
// are undefined. The operands to this are the left and right operands
// to compare (ops #0, and #1) and the condition code to compare them with
// (op #2) as a CondCodeSDNode.
VSETCC,
// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
// integer shift operations, just like ADD/SUB_PARTS. The operation
// ordering is:

26
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -2886,6 +2886,24 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
break;
}
break;
case ISD::VSETCC: {
Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
SDOperand CC = Node->getOperand(2);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
// Everything is legal, see if we should expand this op or something.
switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
case TargetLowering::Custom:
Tmp1 = TLI.LowerOperation(Result, DAG);
if (Tmp1.Val) Result = Tmp1;
break;
}
break;
}
case ISD::SHL_PARTS:
case ISD::SRA_PARTS:
@ -6875,6 +6893,14 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
}
break;
}
case ISD::VSETCC: {
SDOperand LL, LH, RL, RH;
SplitVectorOp(Node->getOperand(0), LL, LH);
SplitVectorOp(Node->getOperand(1), RL, RH);
Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
break;
}
case ISD::ADD:
case ISD::SUB:
case ISD::MUL:

1
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -4383,6 +4383,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::FGETSIGN: return "fgetsign";
case ISD::SETCC: return "setcc";
case ISD::VSETCC: return "vsetcc";
case ISD::SELECT: return "select";
case ISD::SELECT_CC: return "select_cc";
case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";

71
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -685,6 +685,8 @@ public:
void visitAShr(User &I) { visitShift(I, ISD::SRA); }
void visitICmp(User &I);
void visitFCmp(User &I);
void visitVICmp(User &I);
void visitVFCmp(User &I);
// Visit the conversion instructions
void visitTrunc(User &I);
void visitZExt(User &I);
@ -2342,6 +2344,75 @@ void SelectionDAGLowering::visitFCmp(User &I) {
setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
}
void SelectionDAGLowering::visitVICmp(User &I) {
ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
predicate = IC->getPredicate();
else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
predicate = ICmpInst::Predicate(IC->getPredicate());
SDOperand Op1 = getValue(I.getOperand(0));
SDOperand Op2 = getValue(I.getOperand(1));
ISD::CondCode Opcode;
switch (predicate) {
case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
default:
assert(!"Invalid ICmp predicate value");
Opcode = ISD::SETEQ;
break;
}
setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
}
void SelectionDAGLowering::visitVFCmp(User &I) {
FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
predicate = FC->getPredicate();
else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
predicate = FCmpInst::Predicate(FC->getPredicate());
SDOperand Op1 = getValue(I.getOperand(0));
SDOperand Op2 = getValue(I.getOperand(1));
ISD::CondCode Condition, FOC, FPC;
switch (predicate) {
case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
default:
assert(!"Invalid VFCmp predicate value");
FOC = FPC = ISD::SETFALSE;
break;
}
if (FiniteOnlyFPMath())
Condition = FOC;
else
Condition = FPC;
MVT::ValueType DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
}
void SelectionDAGLowering::visitSelect(User &I) {
SDOperand Cond = getValue(I.getOperand(0));
SDOperand TrueVal = getValue(I.getOperand(1));

1
lib/Target/TargetSelectionDAG.td
View File

@ -337,6 +337,7 @@ def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
def select : SDNode<"ISD::SELECT" , SDTSelect>;
def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;