6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-21 18:29:46 +00:00
Code Issues Projects Releases Wiki Activity

Change swift/vldm test case to be less dependent on allocation order

Browse Source 
'Force' values in registers using the calling convention. Now, we only depend on
the calling convention and that the allocator performs copy coalescing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189985 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer 2013-09-04 20:51:06 +00:00
parent 775079c227
commit b4b7a52ec5
1 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
test/CodeGen/ARM/swift-vldm.ll
View File

@ -4,25 +4,25 @@
; so that there usage becomes unbeneficial on swift.
; CHECK-LABEL: test_vldm
; CHECK: vldmia r1, {d18, d19, d20}
; CHECK-NOT: vldmia r1, {d17, d18, d19, d20}
; CHECK: vldmia r{{[0-9]+}}, {d2, d3, d4}
; CHECK-NOT: vldmia r{{[0-9]+}}, {d1, d2, d3, d4}
define double @test_vldm(double %a, double %b, double* nocapture %x) {
declare fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
define void @test_vldm(double* %x, double * %y) {
entry:
%mul73 = fmul double %a, %b
%addr1 = getelementptr double * %x, i32 1
%addr2 = getelementptr double * %x, i32 2
%addr3 = getelementptr double * %x, i32 3
%load0 = load double * %x
%load1 = load double * %addr1
%load2 = load double * %addr2
%load3 = load double * %addr3
%sub = fsub double %mul73, %load1
%mul = fmul double %mul73, %load0
%add = fadd double %mul73, %load2
%div = fdiv double %mul73, %load3
%red = fadd double %sub, %mul
%red2 = fadd double %div, %add
%red3 = fsub double %red, %red2
ret double %red3
%d0 = load double * %y
%d1 = load double * %x
%d2 = load double * %addr1
%d3 = load double * %addr2
%d4 = load double * %addr3
; We are trying to force x[0-3] in register d1 to d4 so that we can test we
; don't form a "vldmia rX, {d1, d2, d3, d4}".
; We are relying on the calling convention and that register allocation
; properly coalesces registers.
call fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
ret void
}