mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-30 05:29:47 +00:00
b4b7a52ec5
'Force' values in registers using the calling convention. Now, we only depend on the calling convention and that the allocator performs copy coalescing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189985 91177308-0d34-0410-b5e6-96231b3b80d8
29 lines
1.1 KiB
LLVM
29 lines
1.1 KiB
LLVM
; RUN: llc < %s -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s
|
|
|
|
; vldm with registers not aligned with q registers need more micro-ops so that
|
|
; so that there usage becomes unbeneficial on swift.
|
|
|
|
; CHECK-LABEL: test_vldm
|
|
; CHECK: vldmia r{{[0-9]+}}, {d2, d3, d4}
|
|
; CHECK-NOT: vldmia r{{[0-9]+}}, {d1, d2, d3, d4}
|
|
|
|
declare fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
|
|
|
|
define void @test_vldm(double* %x, double * %y) {
|
|
entry:
|
|
%addr1 = getelementptr double * %x, i32 1
|
|
%addr2 = getelementptr double * %x, i32 2
|
|
%addr3 = getelementptr double * %x, i32 3
|
|
%d0 = load double * %y
|
|
%d1 = load double * %x
|
|
%d2 = load double * %addr1
|
|
%d3 = load double * %addr2
|
|
%d4 = load double * %addr3
|
|
; We are trying to force x[0-3] in register d1 to d4 so that we can test we
|
|
; don't form a "vldmia rX, {d1, d2, d3, d4}".
|
|
; We are relying on the calling convention and that register allocation
|
|
; properly coalesces registers.
|
|
call fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
|
|
ret void
|
|
}
|