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Add crc32 instruction and intrinsics. Add a new class of prefix
bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78508 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -517,6 +517,10 @@ void Emitter<CodeEmitter>::emitInstruction(
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case X86II::TA: // 0F 3A
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Need0FPrefix = true;
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break;
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case X86II::TF: // F2 0F 38
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MCE.emitByte(0xF2);
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Need0FPrefix = true;
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break;
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case X86II::REP: break; // already handled.
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case X86II::XS: // F3 0F
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MCE.emitByte(0xF3);
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@ -548,6 +552,7 @@ void Emitter<CodeEmitter>::emitInstruction(
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MCE.emitByte(0x0F);
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switch (Desc->TSFlags & X86II::Op0Mask) {
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case X86II::TF: // F2 0F 38
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case X86II::T8: // 0F 38
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MCE.emitByte(0x38);
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break;
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@ -79,6 +79,7 @@ class XD { bits<4> Prefix = 11; }
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class XS { bits<4> Prefix = 12; }
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class T8 { bits<4> Prefix = 13; }
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class TA { bits<4> Prefix = 14; }
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class TF { bits<4> Prefix = 15; }
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class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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string AsmStr>
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@ -229,6 +230,11 @@ class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSE42]>;
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// SS42FI - SSE 4.2 instructions with TF prefix.
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class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TF, Requires<[HasSSE42]>;
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// X86-64 Instruction templates...
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//
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@ -2931,6 +2931,10 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
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case X86II::TA: // 0F 3A
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Need0FPrefix = true;
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break;
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case X86II::TF: // F2 0F 38
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++FinalSize;
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Need0FPrefix = true;
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break;
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case X86II::REP: break; // already handled.
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case X86II::XS: // F3 0F
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++FinalSize;
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@ -2966,6 +2970,9 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
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case X86II::TA: // 0F 3A
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++FinalSize;
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break;
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case X86II::TF: // F2 0F 38
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++FinalSize;
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break;
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}
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// If this is a two-address instruction, skip one of the register operands.
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@ -322,6 +322,9 @@ namespace X86II {
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// T8, TA - Prefix after the 0x0F prefix.
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T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
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// TF - Prefix before and after 0x0F
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TF = 15 << Op0Shift,
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//===------------------------------------------------------------------===//
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// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
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// They are used to specify GPRs and SSE registers, 64-bit operand size,
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@ -3678,3 +3678,75 @@ def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
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(PCMPGTQrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
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(PCMPGTQrm VR128:$src1, addr:$src2)>;
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// crc intrinsic instruction
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// This set of instructions are only rm, the only difference is the size
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// of r and m.
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let Constraints = "$src1 = $dst" in {
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def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
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(ins GR32:$src1, i8mem:$src2),
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"crc32 \t{$src2, $src1|$src1, $src2}",
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[(set GR32:$dst,
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(int_x86_sse42_crc32_8 GR32:$src1,
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(load addr:$src2)))]>, OpSize;
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def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
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(ins GR32:$src1, GR8:$src2),
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"crc32 \t{$src2, $src1|$src1, $src2}",
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[(set GR32:$dst,
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(int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>,
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OpSize;
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def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
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(ins GR32:$src1, i16mem:$src2),
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"crc32 \t{$src2, $src1|$src1, $src2}",
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[(set GR32:$dst,
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(int_x86_sse42_crc32_16 GR32:$src1,
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(load addr:$src2)))]>,
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OpSize;
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def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
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(ins GR32:$src1, GR16:$src2),
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"crc32 \t{$src2, $src1|$src1, $src2}",
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[(set GR32:$dst,
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(int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
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OpSize;
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def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
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(ins GR32:$src1, i32mem:$src2),
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"crc32 \t{$src2, $src1|$src1, $src2}",
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[(set GR32:$dst,
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(int_x86_sse42_crc32_32 GR32:$src1,
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(load addr:$src2)))]>, OpSize;
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def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
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(ins GR32:$src1, GR32:$src2),
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"crc32 \t{$src2, $src1|$src1, $src2}",
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[(set GR32:$dst,
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(int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>,
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OpSize;
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def CRC64m64 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
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(ins GR64:$src1, i64mem:$src2),
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"crc32 \t{$src2, $src1|$src1, $src2}",
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[(set GR64:$dst,
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(int_x86_sse42_crc32_64 GR64:$src1,
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(load addr:$src2)))]>,
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OpSize, REX_W;
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def CRC64r64 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"crc32 \t{$src2, $src1|$src1, $src2}",
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[(set GR64:$dst,
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(int_x86_sse42_crc32_64 GR64:$src1, GR64:$src2))]>,
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OpSize, REX_W;
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// TODO: These correspond to int_x86_sse42_crc32_8 but with a 64-bit src
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// and dest, figure it out.
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//def CRC64m8 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
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// (ins GR32:$src1, i8mem:$src2),
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// "crc32 \t{$src2, $src1|$src1, $src2}",
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// [(set GR64:$dst,
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// (int_x86_sse42_crc32_8 GR64:$src1,
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// (load addr:$src2)))]>,
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// OpSize, REX_W;
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//def CRC64r8 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
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// (ins GR64:$src1, GR8:$src2),
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// "crc32 \t{$src2, $src1|$src1, $src2}",
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// [(set GR64:$dst,
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// (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>,
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// OpSize, REX_W;
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}
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38
test/CodeGen/X86/sse42.ll
Normal file
38
test/CodeGen/X86/sse42.ll
Normal file
@ -0,0 +1,38 @@
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; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X32
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; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64
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declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind
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declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind
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declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind
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define i32 @crc32_8(i32 %a, i8 %b) nounwind {
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%tmp = call i32 @llvm.x86.sse42.crc32.8(i32 %a, i8 %b)
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ret i32 %tmp
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; X32: _crc32_8:
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; X32: crc32 8(%esp), %eax
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; X64: _crc32_8:
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; X64: crc32 %sil, %eax
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}
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define i32 @crc32_16(i32 %a, i16 %b) nounwind {
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%tmp = call i32 @llvm.x86.sse42.crc32.16(i32 %a, i16 %b)
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ret i32 %tmp
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; X32: _crc32_16:
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; X32: crc32 8(%esp), %eax
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; X64: _crc32_16:
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; X64: crc32 %si, %eax
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}
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define i32 @crc32_32(i32 %a, i32 %b) nounwind {
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%tmp = call i32 @llvm.x86.sse42.crc32.32(i32 %a, i32 %b)
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ret i32 %tmp
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; X32: _crc32_32:
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; X32: crc32 8(%esp), %eax
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; X64: _crc32_32:
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; X64: crc32 %esi, %eax
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}
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