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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194661 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
NAKAMURA Takumi 2013-11-14 04:05:22 +00:00
parent 0710afb9af
commit b502e09742
1 changed files with 4 additions and 4 deletions
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8
lib/Target/R600/SIFixSGPRCopies.cpp
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@ -23,9 +23,9 @@
/// %vreg3 <vsrc> = COPY %vreg2 <vgpr>
/// BB2:
/// %vreg4 <vsrc> = PHI %vreg1 <vsrc>, <BB#0>, %vreg3 <vrsc>, <BB#1>
/// %vreg5 <vgpr> = VECTOR_INST %vreg4 <vsrc>
/// %vreg5 <vgpr> = VECTOR_INST %vreg4 <vsrc>
///
///
///
/// The coalescer will begin at BB0 and eliminate its copy, then the resulting
/// code will look like this:
///
@ -43,7 +43,7 @@
/// Now that the result of the PHI instruction is an SGPR, the register
/// allocator is now forced to constrain the register class of %vreg3 to
/// <sgpr> so we end up with final code like this:
///
///
/// BB0:
/// %vreg0 <sgpr> = SCALAR_INST
/// ...
@ -55,7 +55,7 @@
/// %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <sgpr>, <BB#1>
/// %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr>
///
/// Now this code contains an illegal copy from a VGPR to an SGPR.
/// Now this code contains an illegal copy from a VGPR to an SGPR.
///
/// In order to avoid this problem, this pass searches for PHI instructions
/// which define a <vsrc> register and constrains its definition class to